PMU Analog Layout Design Intern (m/f/d) - Munich, Germany
Originally posted 1 September 2026 by the employer.
Support the Power Management team in developing analog ICs.
About the role
This role involves supporting custom analog layout within the Silicon Engineering team, gaining hands-on experience in chip design.
What you'll do
- Support transistor-level layout of analog circuit blocks.
- Assist with layout verification (DRC, LVS, PERC, DFM) using Siemens EDA (Calibre).
- Gain insight into block- and top-level floor-planning.
- Analyze and document layout results and support design reviews.
- Learn layout techniques for device matching, minimizing parasitics, and power routing.
What you'll need
- Currently enrolled student in Electrical Engineering, Microelectronics, or a related field.
- Basic knowledge of semiconductor technology / CMOS circuits.
- Basic familiarity with Unix/Linux command-line environments.
- English language fluency (both written and verbal).
Nice to have
- Initial exposure to layout tools such as Cadence Virtuoso or similar full-custom environments.
Skills: transistor-level layout, analog circuit blocks, layout verification, DRC, LVS, PERC, CMOS technologies
This role has been open 28 days — slightly above the 25-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
49
|
Median days open
25 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (49 roles · 21 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 49 |
| Open roles in the wider Analog & Mixed-Signal family | 39 | 1385 · 107 employers |
| Median days open | 28 d | 25 d (+3 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: transistor-level layout, analog circuit blocks, layout verification, DRC, LVS, PERC, CMOS technologies
Who's hiring in this category
- Celero · 8 open roles · median 32 d
- Analog Devices · 7 open roles · median 12 d
- Marvell Technology · 4 open roles · median 16 d
- Broadcom · 3 open roles · median 8 d
- onsemi · 3 open roles · median 35 d
- QORVO · 3 open roles · median 33 d
How we counted: 49 open Analog IC Design (Analog Layout) roles from 21 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.