PLL Design/ Integration Staff Engineer - Adaptive Computing Group - CA, San Jose, United States

Originally posted 28 July 2026 by the employer.

This role focuses on the design, integration, and characterization of Phase-Locked Loops (PLLs) for FPGA products.

About the role

This Staff Design Engineer role involves leading and contributing to the design, integration, and characterization of Phase-Locked Loops (PLLs) for FPGA products. The position focuses on implementing programmable clocking solutions across AMD's expanding portfolio of Adaptive Embedded Computing products.

What you'll do

• Architect and integrate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters), LDO, Phase Interpolator, High Speed Divider into FPGA products.
• Lead the integration of different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range.
• Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization for Jitter optimization.
• Supervise and verify layouts produced by PD engineers to ensure floor planning, matching, and parasitic minimization using advanced node technologies.
• Conduct comprehensive system-level simulations and validation for PLL IP integration in an FPGA environment using Vivado or similar tools/flows.

What you'll need

• Solid foundation in IC design and manufacturing, including experience with analog/digital IP integration (e.g., PLLs, LDOs, Phase Interpolators), chip design, silicon processes, and packaging technologies.
• Strong understanding of device physics, reliability, and silicon chip manufacturing.
• Experience with modern adaptive computing architectures and post-silicon validation and characterization.
• Advanced degree (MS) in electrical & electronics engineering, or a bachelor's degree with several years of relevant industry experience.

Nice to have

• Experience designing fractional-N PLLs, All-Digital PLLs (ADPLL) and/or sub-sampling PLLs.
• Familiarity with fundamental analog building blocks such as LDOs, bias generators, and operational amplifiers.
• Background in digital design, digital verification, and SystemVerilog modeling.
• Knowledge of clock synthesis and recovery techniques, including PLLs, DLLs, and CDRs.

Skills: PLL, VCOs, charge pumps, jitter, analog/mixed-signal blocks