Physical Layer Architecture Engineer
Originally posted 21 July 2026 by the employer.
About the role
This role involves defining the architecture for the physical layer of NVIDIA's networking products, focusing on both hardware circuitry and supporting firmware/software for high-speed communication in ASICs.
What you'll do
- Lead projects, translating customer requirements into detailed technical specifications for hardware architecture, system embedded software, and user interface.
- Define the architecture for implementing physical layer standards into NVIDIA's ASIC devices.
- Define features for the physical layer to enable interoperability between different generations of communication.
- Be involved in product definition and the high-speed protocols that NVIDIA networking devices will support.
- Work with multi-functional teams (design, backend, system, marketing, firmware, driver) to provide architecture definitions and converge on key design decisions.
What you'll need
- BS or MS degree in EE.
- 3+ years of experience in Physical layer communication, System, Signal Integrity, or high speed communication protocols.
- Background in embedded software.
- Experience in networking.
- Experience in Wire Line Physical layer protocols like IEEE 802.3, InfiniBand, PCIe, USB.
Skills: physical layer communication, high speed communication protocols, PCIe, USB, IEEE 802.3
This role has been open 71 days — below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 30 | 1385 · 108 employers |
| Median days open | 116 d | 76 d (+40 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: physical layer communication, high speed communication protocols, PCIe, USB, IEEE 802.3
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA (this employer) · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.