Physical Design PnR Tile Lead - ON, Markham-33CV, Canada
Originally posted 23 September 2026 by the employer.
About the role
This role involves leading the physical implementation and execution of complex SoC designs at advanced process nodes, combining technical expertise with leadership across multiple programs, engineers, and cross-functional teams.
What you'll do
- Lead physical implementation of complex SoC tiles from floorplan through tapeout.
- Drive overall Tile PnR strategy including floorplanning, placement, CTS, routing, timing closure, congestion management, IR/EM closure, and signoff readiness.
- Own execution planning, milestones, risk management, and quality metrics for critical IPs and SoC tiles.
- Coordinate activities across Design, Timing, CAD, Methodology, Full Chip Floorplan, Power, and Verification teams.
- Mentor and develop Tile PnR engineers across multiple experience levels.
- Drive adoption of new implementation methodologies, automation, and AI-enabled design solutions.
What you'll need
- BS/MS in Electrical Engineering, Computer Engineering, or related field.
- Industry experience in physical design.
- Demonstrated technical leadership across multiple projects or product families.
- Multiple successful tape-outs at advanced technology nodes.
- Proven experience leading critical tiles or IPs.
- Recognized expert in Tile PnR and physical implementation.
- Expertise in congestion analysis, timing architecture, power optimization, and PPA improvement.
- Experience with AI-assisted implementation methodologies.
Nice to have
- Experience leading globally distributed engineering teams.
- Familiarity with ICC2, Innovous, Fusion Compiler, PrimeTime, RedHawk/Totem, Calibre, and related implementation flows.
- Working knowledge of IREM is considered a strong plus.
Skills: Place & Route, PnR, physical implementation, floorplanning, timing closure
This role has been open 0 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
630
|
Median days open
61 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (630 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 37 | 630 |
| Open roles in the wider Physical Implementation family | 62 | 1417 · 108 employers |
| Median days open | 34 d | 61 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Place & Route, PnR, physical implementation, floorplanning, timing closure
Who's hiring in this category
- Qualcomm · 123 open roles · median 37 d
- NVIDIA · 39 open roles · median 48 d
- Broadcom · 38 open roles · median 73 d
- AMD (this employer) · 35 open roles · median 43 d
- Synopsys · 27 open roles · median 62 d
- Cadence Design Systems · 23 open roles · median 87 d
How we counted: 630 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 24 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.