Physical Design Lead — Execution - San Jose, California, United States
$231,500 - $341,075 USD yearly
Originally posted 21 September 2026 by the employer — open 0 days.
About the role
This role drives day-to-day physical design execution and delivery for Altera's chips, coordinating across blocks and full-chip integration from floorplan through tapeout.
What you'll do
- Drive day-to-day physical design execution and delivery across blocks and full-chip integration, from floorplan through tapeout.
- Own the schedule and quality bar for physical design execution, identifying risk and driving mitigation.
- Coordinate execution across multiple blocks and design teams, resolving conflicts and dependencies for full-chip closure.
- Engage senior customer technical stakeholders directly, navigating challenging technical conversations with credibility and diplomacy.
- Serve as the escalation point for execution blockers, driving fast resolution under schedule pressure.
- Mentor physical design engineers on execution best practices, prioritization, and schedule management.
What you'll need
- Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
- 12+ years of physical design experience, including a minimum of four full-chip tapeouts at advanced nodes with direct execution ownership.
- Hands-on expertise across the physical design flow: floorplanning, placement, clock-tree synthesis, routing, and timing/power closure.
- Production physical design execution experience at 7nm / 5nm / 3nm / Intel 18A or comparable advanced nodes.
- Hands-on proficiency with Synopsys Fusion Compiler / ICC2 / PrimeTime, Cadence Innovus / Tempus / Voltus, Ansys RedHawk-SC, Siemens Calibre, or equivalent tools.
- Working command of horizontal signoff flows: timing closure (STA), EMIR, physical verification, formal equivalence, and low-power verification.
- Scripting and automation proficiency (Python, Tcl, Perl, or shell) sufficient to build and debug execution tooling.
- Experience driving execution on designs of high complexity with concurrent block teams across multiple sites.
- Demonstrated ability to engage senior customers and navigate challenging technical conversations.
Nice to have
- Experience serving as an implementation lead or execution owner for a full chip or major subsystem.
- Direct experience representing physical design execution in customer-facing technical reviews.
- Working familiarity with PD signoff methodology (EMIR, timing, power) sufficient to partner with methodology teams.
- Experience mentoring or informally leading execution teams without formal management authority.
Skills: physical design, floorplan, timing closure, tapeout, signoff
This role has been open 0 days — well below the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
603
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Altera | All employers we track in this specialty (603 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 14 | 603 |
| Open roles in the wider Physical Implementation family | 25 | 1382 · 107 employers |
| Median days open | 69 d | 60 d (+9 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: physical design, floorplan, timing closure, tapeout, signoff
Who's hiring in this category
- Qualcomm · 108 open roles · median 43 d
- Broadcom · 38 open roles · median 70 d
- NVIDIA · 38 open roles · median 45 d
- AMD · 35 open roles · median 40 d
- Synopsys · 27 open roles · median 59 d
- Renesas Electronics · 25 open roles · median 47 d
How we counted: 603 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.