Physical Design Implementation and STA Lead - San Jose, California, United States
$149,100 - $215,000 USD yearly
Originally posted 17 July 2026 by the employer.
About the role
Lead physical design implementation and static timing analysis activities for complex blocks and SoC subsystems, driving designs from floorplanning through final timing closure. The position supports physical implementation and timing closure for FPGA SoCs across multi-mode multi-corner conditions.
What you'll do
- Lead block-level physical implementation including synthesis, floorplanning, place-and-route, clock tree synthesis (CTS), optimization, and ECO closure. - Support SoC-level physical implementation and collaborate on floorplanning, partitioning, and integration strategies. - Develop and maintain implementation constraints using SDC and UPF to achieve timing, power, and area (PPA) goals. - Perform static timing analysis (STA) and timing closure across multiple process, voltage, and temperature corners (MMMC) using Synopsys PrimeTime or equivalent tools. - Execute signoff activities including IR drop, electromigration (EM), DRC, LVS, antenna, and physical verification. - Develop Tcl and Python automation to streamline physical implementation and timing analysis workflows.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline. - 7+ years of experience in physical design, physical implementation, or SoC backend development for advanced semiconductor products. - 5+ years of experience performing block-level physical implementation including synthesis, floorplanning, place-and-route, clock tree synthesis (CTS), optimization, and ECO closure. - 3+ years of experience performing static timing analysis using Synopsys PrimeTime or equivalent STA tools, including multi-mode multi-corner (MMMC) timing analysis.
Nice to have
- Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline. - 10+ years of experience in physical design and static timing analysis for advanced semiconductor products. - Experience with advanced process technologies including 7nm, 5nm, or below. - Experience with SoC physical implementation and top-level timing closure. - Experience with high-speed interface implementation including PCIe, Ethernet, SerDes, DDR, LPDDR, HBM, or similar technologies.
Skills: floorplanning, place-and-route, clock tree synthesis, static timing analysis, signoff
This role has been open 95 days — well above the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
656
|
Median days open
61 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Altera | All employers we track in this specialty (656 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 656 |
| Open roles in the wider Physical Implementation family | 27 | 1450 · 110 employers |
| Median days open | 95 d | 61 d (+34 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: floorplanning, place-and-route, clock tree synthesis, static timing analysis, signoff
Who's hiring in this category
- Qualcomm · 119 open roles · median 44 d
- AMD · 61 open roles · median 26 d
- Synopsys · 38 open roles · median 35 d
- Intel Corporation · 36 open roles · median 14 d
- NVIDIA · 36 open roles · median 70 d
- Broadcom · 32 open roles · median 100 d
How we counted: 656 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.