Senior OPC R&D Engineer - San Jose, United States
$159,360 - $255,000 USD yearly
Originally posted 20 October 2026 by the employer.
About the role
As a lead OPC R&D Engineer, you will develop, implement, and guide engineers in developing technology solutions to optimize pattern fidelity, process window, and reliability for critical memory patterning layers. You will use software tools to model and correct for optical and other patterning effects while employing DFM and RET solutions.
What you'll do
- Drive the development, implementation, and optimization of OPC models and recipes, including advanced DFM and RET techniques, for critical memory layers. - Lead patterning development through SMO studies, test plate design, and design rule evaluations. - Validate OPC solution tapeout readiness, conduct quality reviews with litho and process integration teams, and resolve hotspot issues with data-driven solutions. - Guide wafer data collection using validation and simulation software tools for OPC verification to optimize mask quality, pattern fidelity, and process window. - Create technical documentation and training to help internal teams deploy OPC tools and methodologies. - Collaborate with design rule, lithography, process integration, tapeout, and mask engineering teams to align the OPC process with chip manufacturing requirements.
What you'll need
- MS or PhD in Physics, Materials Science, Electrical Engineering, Chemical Engineering, or a related science or engineering discipline. - Minimum of 5 years of TD experience in semiconductor patterning technical areas. - Strong understanding of optical proximity effects, resolution enhancement techniques (RET) including SMO (source mask optimization), and DFM methodologies. - Proficiency in OPC and SMO software using tools such as Mentor, Synopsys, or ASML Brion. - Proficiency in scripting languages including Python, TCL, or Perl, and familiarity with C++. - Demonstrated ability to analyze large datasets, perform statistical analysis, and interpret simulation results.
Nice to have
- 7+ years of experience in OPC/RET or related areas delivering patterning solutions. - Understanding of semiconductor manufacturing technologies and the overall chip fabrication process, especially for NAND flash manufacturing.
Skills: OPC, RET, SMO, DFM, photolithography, Python
This role has been open 0 days — well below the 73-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
672
|
Median days open
73 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Solidigm | All employers we track in this specialty (672 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 672 |
| Open roles in the wider Physical Implementation family | 1 | 1441 · 110 employers |
| Median days open | 0 d | 73 d (−73 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: OPC, RET, SMO, DFM, photolithography, Python
Who's hiring in this category
- Cadence Design Systems · 154 open roles · median 169 d
- Synopsys · 64 open roles · median 38 d
- Micron Technology · 45 open roles · median 48 d
- Qualcomm · 36 open roles · median 77 d
- GlobalFoundries · 33 open roles · median 40 d
- Keysight Technologies · 32 open roles · median 74 d
How we counted: 672 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.