Physical Design Engineering, VP - San Jose, California, United States
$250,600 - $375,000 USD yearly
Originally posted 27 July 2026 by the employer — open 45 days.
Astera Labs is driving the physical implementation of multi-die chiplet architectures for rack-scale AI infrastructure.
About the role
What you'll do
- Lead end-to-end physical design execution for complex multi-die switching products with UCIe and UALink connectivity.
- Drive chip-level floorplanning, power planning, placement, routing, and timing closure for advanced node designs.
- Establish physical design methodologies and best practices for interposer-based chiplet architectures and die-to-die interfaces.
- Own physical design quality metrics including timing, power, area, and manufacturability across multiple concurrent projects.
- Scale and develop the physical design organization and mentor Directors, Managers, and senior engineers.
- Partner with architecture, digital design, packaging, and silicon engineering teams to influence RTL for physical implementation success.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
- 15+ years of experience in physical design and implementation of complex SoCs or ASICs.
- Track record leading physical design teams and delivering multiple successful tapeouts in advanced process nodes (7nm or below).
- Expertise in chiplet architectures, interposer design, and die-to-die interface implementation.
- Strong understanding of advanced packaging technologies including 2.5D and 3D integration.
- Expert-level knowledge of physical design flows, timing closure, power optimization, and signoff methodologies.
- Experience managing and scaling engineering teams of 20+ people.
Nice to have
- Master's degree or PhD in Electrical Engineering or related field.
- Experience with UCIe, PCIe Gen 6/7, or other high-speed SerDes physical implementation.
- Background in AI/ML infrastructure, networking ASICs, or high-performance switching products.
- Expertise with Cadence and/or Synopsys physical design tools and flows.
- Experience with advanced DFT integration and design for manufacturability (DFM).
- Track record of innovation in physical design methodologies and automation.
Skills: physical design, multi-die chiplet architectures, floorplanning, timing closure, advanced process nodes
This role has been open 44 days — well below the 57-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
615
|
Median days open
57 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (615 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 17 | 615 |
| Open roles in the wider Physical Implementation family | 22 | 1427 · 104 employers |
| Median days open | 94 d | 57 d (+37 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: physical design, multi-die chiplet architectures, floorplanning, timing closure, advanced process nodes
Who's hiring in this category
- Qualcomm · 99 open roles · median 34 d
- NVIDIA · 42 open roles · median 49 d
- Broadcom · 41 open roles · median 59 d
- AMD · 32 open roles · median 46 d
- Synopsys · 28 open roles · median 62 d
- Intel Corporation · 25 open roles · median 61 d
How we counted: 615 open Physical Design (Physical Design) roles from 74 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.