Physical Design Engineer - Timing Lead
$200,000 - $250,000 USD yearly
Originally posted 20 February 2026 by the employer.
About the role
Efficient Computer is seeking a Physical Design Engineer - Timing Lead to work hands-on on timing convergence and methodology for general-purpose processor designs in FinFET technologies.
What you'll do
- Drive and develop timing flows and methodology from scratch in Cadence Tempus or Synopsys PrimeTime for FinFET and multi-patterning technologies. - Own and drive timing convergence of IP, subsystem, and SoC blocks. - Define timing margining, PVTRC corner definitions, extraction methodology, and signoff timing to SYN/PNR correlation. - Develop slew rate and glitch noise checks, along with custom timing checks for proprietary ultra-low-power architecture. - Work closely with RTL, DFT, and IP vendors to define and drive SDC constraints. - Partner with post-silicon product bring-up teams to verify pre-silicon to post-silicon timing correlation.
What you'll need
- Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience. - Track record of delivering IP/SS or SoC STA sign-off for multiple tape-outs in 12nm or below process technologies. - Experience with EDA flows using Cadence, Synopsys, or Mentor tools for STA and simulations (PrimeTime, HSPICE) with hierarchical design and abstraction techniques. - Hands-on experience in timing convergence of high-frequency and low-power designs. - Expert knowledge of static timing analysis, defining constraints and exceptions, corners/voltage definitions, and timing margining. - Scripting skills in TCL, shell, and Python.
Nice to have
- Knowledge of computer architecture, physical design, and ASIC implementation. - Experience in full-chip sign-off budgeting. - Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology. - Experience building CAD flow infrastructure for physical design engineers. - Experience integrating analog or mixed-signal macros on top-level designs.
Skills: timing convergence, static timing analysis, cadence tempus, synopsys primetime, sdc constraints
This role has been open 129 days — well above the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Efficient Computer | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 673 |
| Open roles in the wider Physical Implementation family | 3 | 1494 · 109 employers |
| Median days open | 105 d | 63 d (+42 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: timing convergence, static timing analysis, cadence tempus, synopsys primetime, sdc constraints
Who's hiring in this category
- Qualcomm · 122 open roles · median 46 d
- AMD · 63 open roles · median 27 d
- Intel Corporation · 40 open roles · median 15 d
- NVIDIA · 38 open roles · median 68 d
- Synopsys · 37 open roles · median 37 d
- Broadcom · 34 open roles · median 102 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.