Physical Design Engineer, Timing - Austin, Texas, United States
$100,000 - $500,000 USD yearly
Originally posted 22 September 2026 by the employer.
This role focuses on timing analysis for high performance RISC-V CPU designs.
About the role
This role involves converging multi-million-gate designs on advanced process nodes and partnering with cross-functional teams through final signoff and tapeout. This includes timing analysis for a high performance RISC-V CPU.
What you'll do
- Drive timing convergence across blocks, partitions, sections, and top-level designs; generate and validate timing models and publish results.
- Analyze timing violations, develop and propagate fixes, and debug timing-flow issues.
- Develop and validate bottom-up constraints while partnering with Design and DFT teams on methodology updates and closure requirements.
- Use Python, Perl, and Tcl for automation and flow development.
What you'll need
- 8+ years of experience in STA, timing closure, and advanced-node design implementation.
- Experience with timing flows, SDC constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff.
- Skilled in writing and debugging SDC constraints, creating ECOs, and developing closure strategies.
- Ability to analyze worst-case corners.
Nice to have
- Experience with SPICE, PNR, placement, CTS, routing, post-route optimization, DFT, or AI-based automation.
Skills: static timing analysis, timing closure, advanced-node design, SDC constraints, tapeout
This role has been open 0 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
633
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Tenstorrent | All employers we track in this specialty (633 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 633 |
| Open roles in the wider Physical Implementation family | 12 | 1414 · 108 employers |
| Median days open | 144 d | 61 d (+83 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: static timing analysis, timing closure, advanced-node design, SDC constraints, tapeout
Who's hiring in this category
- Qualcomm · 122 open roles · median 37 d
- Broadcom · 39 open roles · median 72 d
- NVIDIA · 38 open roles · median 47 d
- AMD · 36 open roles · median 38 d
- Synopsys · 27 open roles · median 61 d
- Renesas Electronics · 25 open roles · median 49 d
How we counted: 633 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 23 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.