Physical Design Engineer, Timing
$100,000 - $500,000 USD yearly
This role focuses on timing analysis for high performance RISC-V CPU designs.
Originally posted 22 September 2026 by the employer.
About the role
This role involves converging multi-million-gate designs on advanced process nodes and partnering with cross-functional teams through final signoff and tapeout. This includes timing analysis for a high performance RISC-V CPU.
What you'll do
- Drive timing convergence across blocks, partitions, sections, and top-level designs; generate and validate timing models and publish results.
- Analyze timing violations, develop and propagate fixes, and debug timing-flow issues.
- Develop and validate bottom-up constraints while partnering with Design and DFT teams on methodology updates and closure requirements.
- Use Python, Perl, and Tcl for automation and flow development.
What you'll need
- 8+ years of experience in STA, timing closure, and advanced-node design implementation.
- Experience with timing flows, SDC constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff.
- Skilled in writing and debugging SDC constraints, creating ECOs, and developing closure strategies.
- Ability to analyze worst-case corners.
Nice to have
- Experience with SPICE, PNR, placement, CTS, routing, post-route optimization, DFT, or AI-based automation.
Skills: static timing analysis, timing closure, advanced-node design, SDC constraints, tapeout
More semiconductor jobs: Tenstorrent jobs · Physical design jobs · Austin jobs
This role has been open 41 days — well below the 62-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
690
|
Median days open
62 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Tenstorrent | All employers we track in this specialty (690 roles · 83 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 690 |
| Open roles in the wider Physical Implementation family | 13 | 1561 · 110 employers |
| Median days open | 185 d | 62 d (+123 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: static timing analysis, timing closure, advanced-node design, SDC constraints, tapeout
Who's hiring in this category
- Qualcomm · 107 open roles · median 55 d
- AMD · 60 open roles · median 35 d
- Broadcom · 43 open roles · median 66 d
- NVIDIA · 42 open roles · median 79 d
- Synopsys · 41 open roles · median 34 d
- Intel Corporation · 31 open roles · median 25 d
How we counted: 690 open Physical Design (Physical Design) roles from 83 employers tracked in the SemiconductorJobs index, counted 3 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.