Physical Design Engineer - Synth, Senior
$200,000 - $300,000 USD yearly
About the role
This role involves owning synthesis, timing convergence, and implementation readiness for key partitions across an AI accelerator roadmap.
What you'll do
- Own synthesis for assigned partitions and subsystems, delivering high-QoR netlists on schedule.
- Develop and improve synthesis flows, including constraint development, timing budgeting, QoR optimization, incremental synthesis, and hierarchical implementation.
- Run hands-on synthesis using Cadence Genus and Synopsys Design Compiler.
- Develop and maintain SDC constraints, including clock definitions, false paths, multicycle paths, generated clocks, and MMMC environments.
- Drive logical timing closure for assigned partitions, optimizing across frequency, area, power, congestion, and wireability.
- Partner with backend implementation engineers on physical-aware synthesis, retiming, register balancing, pipeline optimization, and logic restructuring.
What you'll need
- 8+ years of ASIC implementation experience, including at least two successful tapeouts.
- Strong hands-on proficiency in synthesis and flow development.
- Proven experience closing timing on complex, multi-million-gate designs.
- Deep working knowledge of Cadence Genus and/or Synopsys Design Compiler.
- Strong SDC expertise, including constraint development and MMMC environments.
- Hands-on experience with advanced process nodes (7nm and below).
- Strong Tcl and Python scripting ability for automation and flow development.
Nice to have
- Experience with AI accelerators, CPUs, or GPUs.
- Experience at 5nm and below.
- Familiarity with LPDDR, PCIe, or SerDes interfaces.
- Exposure to chiplet-based architectures and multi-clock SoC designs.
- Experience mentoring junior engineers or leading synthesis for a subsystem.
Skills: synthesis, timing closure, Cadence Genus, Synopsys Design Compiler, SDC
More semiconductor jobs: Physical design jobs
This role has been open 39 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
717
|
Median days open
59 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Positron AI | All employers we track in this specialty (717 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 717 |
| Open roles in the wider Physical Implementation family | 3 | 1606 · 116 employers |
| Median days open | 59 d | 59 d (same as this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: synthesis, timing closure, Cadence Genus, Synopsys Design Compiler, SDC
Who's hiring in this category
- Qualcomm · 104 open roles · median 59 d
- AMD · 63 open roles · median 40 d
- Broadcom · 47 open roles · median 19 d
- NVIDIA · 45 open roles · median 81 d
- Synopsys · 44 open roles · median 38 d
- Intel Corporation · 32 open roles · median 30 d
How we counted: 717 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.