Physical Design Engineer Intern, BS - Summer 2027 - United States
$29 - $57 USD yearly
Originally posted 5 September 2026 by the employer.
About the role
This internship involves working within Physical Design teams that implement ASIC and processor designs or focus on timing analysis for high-performance data center chips.
What you'll do
- Perform synthesis, floor planning, place and route, clock insertion, timing analysis, and timing closure on complex logic blocks.
- Write scripts in Python, TCL, Perl, and Shell to support design and development activities.
- Analyze, debug, and implement fixes for design violations using CAD tools.
- Collaborate with RTL, Synthesis, and other Design teams to resolve congestion and timing bottlenecks.
What you'll need
- Currently enrolled in a Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field with an expected graduation date between Fall 2027 – Summer 2028.
- Completed courses focusing on VLSI, digital logic, circuit design, computer architecture, RTL synthesis, Verilog or SystemVerilog, place and route, static timing analysis, digital systems, or microelectronics.
- Proficiency in programming and scripting languages like Python, TCL, Perl, and Shell.
- Experience working in a Unix type environment.
- Experience using tools like Synopsys (PrimeTime), Cadence (Tempus), and Mentor.
Skills: synthesis, floor planning, place and route, clock insertion, timing analysis, timing closure
This role has been open 24 days — well below the 64-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
627
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (627 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 627 |
| Open roles in the wider Physical Implementation family | 16 | 1419 · 109 employers |
| Median days open | 46 d | 64 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: synthesis, floor planning, place and route, clock insertion, timing analysis, timing closure
Who's hiring in this category
- Qualcomm · 114 open roles · median 40 d
- AMD · 44 open roles · median 28 d
- Broadcom · 40 open roles · median 78 d
- NVIDIA · 38 open roles · median 53 d
- Synopsys · 27 open roles · median 56 d
- NXP Semiconductors · 25 open roles · median 77 d
How we counted: 627 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.