Physical Design Engineer, Hardware - Palo Alto, CA
$200,000 - $420,000 USD yearly
Originally posted 15 May 2026 by the employer.
About the role
You will own the physical implementation flow from synthesis through tape-out, handling block-level and top-level physical design to maximize PPA on advanced foundry nodes. This work supports timing, electrical, and physical verification closure for a custom AI accelerator.
What you'll do
- Own the physical implementation flow from RTL synthesis through placement, clock tree synthesis (CTS), and routing for high-performance blocks. - Optimize layout topologies to maximize cell density and utilization, architecting power delivery networks (PDN) to minimize IR drop and meet frequency targets on advanced foundry nodes. - Conduct static timing analysis (STA), fix setup/hold violations across complex clock domains, and resolve signal integrity (SI), electromigration (EM), and IR-drop constraints. - Run and debug sign-off physical verification, including Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Antenna rule compliance. - Partner with RTL designers to provide physical feedback on logic structures, pipeline depth, and routing congestion. - Integrate and develop AI-driven EDA tools and workflows to optimize the physical implementation cycle and design closure.
What you'll need
- Bachelor’s degree in Electrical Engineering or Computer Engineering, with 5+ years of practical industry experience working with advanced process nodes (7nm or below). - Hands-on proficiency with industry-standard physical design, timing, and sign-off tools such as Innovus, Fusion Compiler, PrimeTime, and RedHawk. - Proven track record running logic synthesis, integrating compiled memory macros, and managing multi-voltage design techniques using power intent specifications (UPF/CPF). - Debugging skills focused on navigating trade-offs between congestion, timing slack, and power density in highly utilized designs.
Nice to have
- Experience delivering high-performance SoCs, CPUs, GPUs, or AI accelerators through multiple production tape-outs. - Experience optimizing physical layouts for highly parallel compute structures, including systolic arrays, large tensor execution units, or high-bandwidth memory (HBM) interfaces. - Experience custom-scripting or extending EDA tools using Tcl, Python, or specialized ML APIs to automate physical design closure and build workflow pipelines.
Skills: synthesis, place-and-route, static timing analysis, physical verification, advanced foundry nodes, AI accelerator
This role has been open 130 days — well above the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | River | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 673 |
| Open roles in the wider Physical Implementation family | 1 | 1494 · 109 employers |
| Median days open | 130 d | 63 d (+67 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: synthesis, place-and-route, static timing analysis, physical verification, advanced foundry nodes, AI accelerator
Who's hiring in this category
- Qualcomm · 122 open roles · median 46 d
- AMD · 63 open roles · median 27 d
- Intel Corporation · 40 open roles · median 15 d
- NVIDIA · 38 open roles · median 68 d
- Synopsys · 37 open roles · median 37 d
- Broadcom · 34 open roles · median 102 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.