Physical Design Engineer
$101,400 - $152,200 USD yearly
Originally posted 2 November 2026 by the employer.
About the role
Qualcomm is seeking Physical Design Engineers to work on ASIC and SoC development across floorplanning, Clock Tree Synthesis, low power implementation, timing analysis, and design methodology. Engineers will execute physical design flows from synthesized netlist to tape-out for complex, high-speed, and low-power designs.
What you'll do
- Execute and drive all stages of the physical design flow from synthesized netlist to tape-out for complex, high-speed, and low-power ASICs and SoCs.
- Perform floorplanning, partitioning, power planning, and IR-drop analysis.
- Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
- Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
- Perform RC extraction, physical verification, formal verification, and implement engineering change orders (ECOs) through sign-off.
- Develop automation and productivity tools using scripting languages and software development techniques.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- 2-10 years of industry experience or relevant academic/project experience in Physical Design.
Nice to have
- ASIC/SoC Physical Design implementation experience.
- Place and Route experience using Cadence Innovus and/or Synopsys Fusion Compiler.
- Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
- Physical verification, design sign-off methodologies, and formal verification techniques and tools.
- Experience with Clock Tree Synthesis (CTS), routing, timing optimization, power domain implementation, and low-power design methodologies.
- Signal integrity, noise analysis, MMMC sign-off flows, and DFT-aware physical implementation.
- Programming and automation using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
Skills: Place and Route, Innovus, PrimeTime, CTS, STA
More semiconductor jobs: Qualcomm jobs · Physical design jobs · San Diego jobs
This role has been open 0 days — well below the 62-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
690
|
Median days open
62 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (690 roles · 83 employers) |
|---|---|---|
| Open roles in this specialty | 108 | 690 |
| Open roles in the wider Physical Implementation family | 152 | 1558 · 110 employers |
| Median days open | 55 d | 62 d (−7 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Place and Route, Innovus, PrimeTime, CTS, STA
Who's hiring in this category
- Qualcomm (this employer) · 107 open roles · median 55 d
- AMD · 60 open roles · median 35 d
- Broadcom · 43 open roles · median 66 d
- NVIDIA · 42 open roles · median 79 d
- Synopsys · 41 open roles · median 34 d
- Intel Corporation · 31 open roles · median 25 d
How we counted: 690 open Physical Design (Physical Design) roles from 83 employers tracked in the SemiconductorJobs index, counted 3 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.