Lead C++ Software Engineer - Palladium Emulation Platform
$119,000 - $221,000 USD yearly
Develop emulator compiler software for the Cadence Palladium Platform.
Originally posted 3 November 2026 by the employer.
About the role
Cadence Design Systems is seeking a Lead C++ Software Engineer to contribute to emulator compiler development for the Cadence Palladium Platform. The role focuses on applying multi-threading and distributed computing to solve large-scale compile problems, including logic optimization, partitioning, and scheduling.
What you'll do
- Develop emulator compiler software for the Cadence Palladium Platform in San Jose, CA.
- Apply multi-threading and distributed computing techniques to address large-scale compile challenges.
- Implement software solutions for logic optimization, partitioning, and scheduling.
- Debug and optimize complex software systems using gdb within Linux/Unix development environments.
What you'll need
- MS with 2 years of experience or a Ph.D. in engineering, computer science, or a related field.
- Strong understanding of data structures, algorithms, and databases.
- Demonstrated proficiency in C++, gdb debugging, and general software development skills.
- Familiarity with Linux/Unix development.
- Exposure to build and version-control systems.
- Coursework in Hardware Description Languages, such as Verilog, SystemVerilog, or VHDL.
- Exposure to electronic design platforms.
Skills: C++, Palladium, Emulation, Verilog, gdb, algorithms
More semiconductor jobs: Cadence Design Systems jobs · EDA tools engineer jobs
This role has been open 0 days — well below the 63-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
724
|
Median days open
63 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (724 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 159 | 724 |
| Open roles in the wider Physical Implementation family | 192 | 1558 · 110 employers |
| Median days open | 158 d | 63 d (+95 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: C++, Palladium, Emulation, Verilog, gdb, algorithms
Who's hiring in this category
- Cadence Design Systems (this employer) · 158 open roles · median 159 d
- Synopsys · 59 open roles · median 49 d
- Micron Technology · 49 open roles · median 41 d
- NVIDIA · 40 open roles · median 125 d
- Renesas Electronics · 38 open roles · median 11 d
- Qualcomm · 34 open roles · median 84 d
How we counted: 724 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 3 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.