$175,000 - $263,300 USD yearly
About the role
Apple is seeking a Physical Design Engineer in San Diego, California, to build full chip clock trees, automate clock specifications, and complete netlist to GDS2 implementation across partitions.
What you'll do
- Build full chip clock trees, perform specification generation, and handle clock planning involving the design and construction of recombinant networks.
- Automate clock tree specification generation for clock construction and distribution across dies to meet clock tree specifications, latency, and power targets.
- Collaborate with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
- Complete netlist to GDS2 implementation for partitions while meeting schedule and design goals.
- Conduct timing, physical, and electrical verification, and drive signoff closure for the partitions.
- Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
What you'll need
- Master’s degree (or foreign equivalent) in Computer Engineering, Electrical Engineering, or a related field, plus 2 years of experience in the job offered or a related occupation.
- Experience building clock networks for high-performance CPU cores to ensure minimal latency.
- Experience analyzing interconnect delays, parasitics, and coupling, and understanding their impact on system performance.
- Experience optimizing interconnect wire delays for dynamic power performance.
- Experience performing physical design with FinFET and GAA standard cell technologies to achieve optimal performance, power, and area.
- Experience building full chip clock trees, specification generation, and clock planning involving recombinant networks.
- Experience automating clock tree specification generation for clock construction and distribution across dies to meet latency and power specifications.
- Experience utilizing industry-standard EDA tools from Synopsys or Cadence with an understanding of their underlying algorithms.
- Experience with static timing analysis, physical design verification analysis, and place and route methodology to achieve optimal PPA.
Skills: clock tree synthesis, PPA, place and route, STA, FinFET, Cadence/Synopsys
More semiconductor jobs: Apple jobs · Physical design jobs
This role has been open 0 days — well below the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
708
|
Median days open
63 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (708 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 708 |
| Open roles in the wider Physical Implementation family | 32 | 1603 · 117 employers |
| Median days open | 10 d | 63 d (−53 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: clock tree synthesis, PPA, place and route, STA, FinFET, Cadence/Synopsys
Who's hiring in this category
- Qualcomm · 109 open roles · median 57 d
- AMD · 61 open roles · median 37 d
- Broadcom · 49 open roles · median 37 d
- NVIDIA · 45 open roles · median 78 d
- Synopsys · 43 open roles · median 36 d
- Intel Corporation · 33 open roles · median 27 d
How we counted: 708 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.
