Physical Design - CAD Lead
$180,000 - $220,000 USD yearly
Originally posted 20 February 2026 by the employer.
About the role
Efficient Computer is seeking a CAD Lead to build and manage Physical Design flows and infrastructure from scratch in a newly formed hardware engineering organization. The role supports physical design for FinFET and multi-patterning technologies across energy-efficient edge AI computing product lines.
What you'll do
- Drive and develop PD flows and methodology from scratch for FinFET and multi-patterning technologies using Cadence Tempus or Synopsys PrimeTime. - Develop repeatable, predictable, design and process-agnostic PD flows alongside flow infrastructure for multiple product lines. - Partner with PD team leads to propose and build end-to-end build and signoff flows. - Build regression frameworks to ensure flow quality and develop collateral quality checking utilities. - Deploy a unified environment specifying all collaterals (stdcell, memory, PDK, hard IPs) and flow dependencies, including PVTRC corners and process configurations. - Coordinate work with third-party vendor resources and drive continuous improvements in flow consistency.
What you'll need
- Master's degree in Electrical Engineering with 5+ years of industry experience, or a PhD with 3+ years of experience. - Strong scripting skills in Python, TCL, and shell. - Experience developing workflow orchestration infrastructure or tools for hardware development, such as Airflow or FlowTracer. - Familiarity with Kubernetes and containerization. - Experience implementing regression frameworks and proficiency with databases such as SQL or MongoDB. - Intimate knowledge of hardware design workflows for Physical Design and RTL/DV.
Nice to have
- Experience in full-chip RTL/DV and PD flows. - Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and their implications for physical design. - Experience defining design constraints for static timing analysis across synthesis, pre/post-CTS, and sign-off, as well as corners and voltage definitions. - Experience integrating analog or mixed-signal macros on top-level designs. - Experience verifying IP collaterals.
Skills: PD flows, methodology, Cadence Tempus, Synopsys Primetime, Python scripting, workflow orchestration
This role has been open 129 days — well above the 70-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
696
|
Median days open
70 d
|
Median salary
$193k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Efficient Computer | All employers we track in this specialty (696 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 696 |
| Open roles in the wider Physical Implementation family | 3 | 1494 · 109 employers |
| Median days open | 129 d | 70 d (+59 d vs this employer) |
| Median salary (USD postings) | — | $193k |
Skills observed across this category: PD flows, methodology, Cadence Tempus, Synopsys Primetime, Python scripting, workflow orchestration
Who's hiring in this category
- Cadence Design Systems · 155 open roles · median 150 d
- Synopsys · 63 open roles · median 41 d
- Micron Technology · 46 open roles · median 50 d
- GlobalFoundries · 38 open roles · median 24 d
- Qualcomm · 37 open roles · median 74 d
- Keysight Technologies · 34 open roles · median 77 d
How we counted: 696 open EDA/CAD Engineering (EDA Tools) roles from 76 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.