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NVIDIA

Physical Design and Timing Engineer Intern - Summer 2027 - CA, Santa Clara, United States

NVIDIA US, CA, Santa Clara, United States Internship 20 days ago
Physical Design & EDA

$20 - $71 USD yearly

Originally posted 15 September 2026 by the employer — open 4 days.

About the role

This internship involves contributing to physical design and timing closure activities for high-frequency and low-power designs.

What you'll do

  • Drive physical design, power, and timing closure.
  • Help drive frontend and backend implementation from RTL to GDSII.
  • Run physical design experiments.
  • Help develop flows and methodologies.

What you'll need

  • Pursuing an MS or Ph.D. in Electrical or Computer Engineering.
  • Familiarity with applying AI/ML techniques to physical design workflows.
  • Knowledge of or experience with Static Timing Analysis (STA), power analysis, and power reduction.
  • Experience in logic synthesis and equivalence checking.
  • Experience with physical optimization, e.g., placement, routing, clock tree.
  • Background in industry-standard EDA tools (e.g., Cadence, Synopsys, Siemens).
  • Proficiency in programming and scripting languages such as Perl, Tcl, Make, Python.

Skills: physical design, power and timing closure, RTL to GDSII, Static Timing Analysis, placement, routing, clock tree

Market context

This role has been open 3 days — well below the 58-day median for Physical Design roles.

Physical Design · Physical Design

Open roles in category
603
Median days open
58 d
Median salary
$185k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How NVIDIA compares in Physical Design hiring
Metric NVIDIA All employers we track in this specialty (603 roles · 78 employers)
Open roles in this specialty 39 603
Open roles in the wider Physical Implementation family 93 1371 · 106 employers
Median days open 43 d 58 d (−15 d vs this employer)
Median salary (USD postings) — $185k

Skills observed across this category: physical design, power and timing closure, RTL to GDSII, Static Timing Analysis, placement, routing, clock tree

Who's hiring in this category

  • Qualcomm · 108 open roles · median 41 d
  • Broadcom · 38 open roles · median 68 d
  • NVIDIA (this employer) · 38 open roles · median 49 d
  • AMD · 35 open roles · median 38 d
  • Synopsys · 27 open roles · median 57 d
  • Renesas Electronics · 25 open roles · median 45 d

How we counted: 603 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.

Apply now
US, CA, Santa Clara, United States
On-site
Internship
$20 - $71 USD yearly
20 days ago

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