Physical Design and CAD Engineer
$160,000 - $200,000 USD yearly
Originally posted 6 November 2026 by the employer.
About the role
As a Physical Design and CAD Engineer, you will serve as a Technical Lead developing connectivity ASICs for cloud and AI infrastructure. This role combines Physical Design CAD methodology development with hands-on place-and-route (PNR) implementation, timing closure, and GDSII signoff.
What you'll do
- Develop and maintain Physical Design CAD flows and methodologies for advanced process nodes.
- Build automation frameworks using Python and Tcl to support synthesis through signoff.
- Perform hands-on Physical Design and PNR, including floorplanning, placement, CTS, routing, and timing closure.
- Develop and optimize EDA tool flows for timing analysis, extraction, EM/IR, and physical verification.
- Support block-level implementation from synthesis through GDSII signoff.
- Collaborate with design, verification, and engineering teams to support ASIC development and tapeout.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
- 5+ years of experience in ASIC Physical Design, CAD methodology, or design automation.
- Strong understanding of physical design implementation and RTL-to-GDSII methodologies.
- Hands-on experience with PNR, timing closure, and physical design signoff.
- Proficiency in Python and/or Tcl scripting.
- Experience with Cadence and/or Synopsys physical design tools.
- Experience with advanced semiconductor process nodes (7nm or below).
Nice to have
- Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience with 3nm or more advanced process technologies.
- Experience building automated CAD flows from synthesis through signoff.
- Familiarity with Cadence Innovus, Tempus, Genus, Synopsys ICC2, Fusion Compiler, and PrimeTime.
- Experience with EM/IR analysis, DRC/LVS, ECO, and timing signoff methodologies.
- Experience with block-level ownership through tapeout.
- Experience developing scalable CAD methodologies and automation frameworks.
Skills: PNR, CAD flows, timing closure, Tcl, Innovus, PrimeTime
More semiconductor jobs: Astera Labs jobs · Physical design jobs · San Jose jobs
This role has been open 0 days — well below the 58-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
720
|
Median days open
58 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (720 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 720 |
| Open roles in the wider Physical Implementation family | 29 | 1612 · 116 employers |
| Median days open | 25 d | 58 d (−33 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: PNR, CAD flows, timing closure, Tcl, Innovus, PrimeTime
Who's hiring in this category
- Qualcomm · 105 open roles · median 59 d
- AMD · 64 open roles · median 39 d
- Broadcom · 49 open roles · median 39 d
- NVIDIA · 45 open roles · median 80 d
- Synopsys · 43 open roles · median 38 d
- Intel Corporation · 32 open roles · median 29 d
How we counted: 720 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 7 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.