PD Leadership role - Bangalore-Technostar B3, India
Originally posted 22 September 2026 by the employer.
About the role
This role involves leading the physical design implementation and convergence activities from RTL2GDSII for high-performance SOCs/ASICs within AMD's S3 India physical design team.
What you'll do
- Lead and mentor convergence of complex tiles/partitions/blocks across multiple subsystems and IPs (e.g., PCIe, DDR, CPUs, GPUs, Gfx, ETH, UCIE).
- Drive physical design implementation, timing closure, and various sign-off activities (timing, physical verification, IREM, Power).
- Provide strategic direction for SOC/Subsystem and Tile/Partition level execution, aligned with industry trends.
- Collaborate with architecture, design, verification, DFT, and product management teams to achieve PPA goals.
- Drive methodology development and adopt latest flows/methodologies and AI technologies.
- Define and track key performance indicators (KPIs) related to RTL2GDSII, reporting progress to senior leadership.
What you'll need
- 15+ years of industry experience in Physical Design (RTL to GDS, STA, Physical verification, timing sign-off, tape-out).
- Experience with SOC and Block-level implementation, including Floorplanning, Timing Closure, and Physical Verification.
- Proficiency in Physical Design verification sign-off techniques such as Formal Equivalence, IR&EM, Timing Closure (STA), Physical verification, VSI, Formal Equivalence Check or LEC.
- Expert level understanding of Power, Performance and Area (PPA) optimization techniques.
- Hands-on experience with Perl/TCL/Shell/Python scripting and Verilog/VHDL RTL design, including AI technologies.
- Ability to drive/manage projects from RTL to GDS, with experience managing 5-10+ tape-outs.
- Proficient in physical design industry-standard EDA tools like Fusion compiler/ICC2/Primetime/Redhawk/PTPX, low power and physical verification tools.
Nice to have
- Expert level understanding of EDA tools across Synopsys and Cadence.
- Good understanding of foundry DRM and collaboration with DTCO and FTO.
- B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering.
Skills: RTL2GDSII, Physical Design, Timing closure, PnR, Physical Verification
This role has been open 0 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
633
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (633 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 36 | 633 |
| Open roles in the wider Physical Implementation family | 62 | 1414 · 108 employers |
| Median days open | 38 d | 61 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL2GDSII, Physical Design, Timing closure, PnR, Physical Verification
Who's hiring in this category
- Qualcomm · 122 open roles · median 37 d
- Broadcom · 39 open roles · median 72 d
- NVIDIA · 38 open roles · median 47 d
- AMD (this employer) · 36 open roles · median 38 d
- Synopsys · 27 open roles · median 61 d
- Renesas Electronics · 25 open roles · median 49 d
How we counted: 633 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 23 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.