Originally posted 22 September 2026 by the employer.
About the role
As a member of the S3 India physical design team, you will help bring to life designs in a leadership capacity, focusing on high-performance SOCs/ASICS for DPU/APU/GPU/Others designs.
What you'll do
- Be the subject matter expert for multiple SOC/ASICs in the RTL2GDSII domain, including physical design implementation, timing closure, and various sign-off activities.
- Provide leadership and mentorship for convergence of complex tiles/partitions/blocks across multiple Subsystems and IPs (e.g., PCIE, DDR, CPUs, GPUs, Gfx, ETH, UCIE).
- Collaborate with cross-functional teams (architecture, design, verification, DFT, product management) to achieve PPA goals.
- Provide strategic direction for SOC/Subsystem and Tile/Partition level execution.
- Drive methodology development and internal forums for adopting latest flows/methodologies and AI technologies.
- Define and track key performance indicators (KPIs) related to RTL2GDSII, reporting progress to leadership.
What you'll need
- 15+ years of industry experience in Physical design (RTL to GDS, STA, Physical verification, timing signoff, tapeout).
- Experience with SOC and Block-level implementation, including Floorplanning, Timing Closure, and Physical Verification.
- Proficiency in Physical Design verification sign-off techniques such as Formal Equivalence, IR&EM, Timing Closure (STA), Physical verification, VSI, Formal Equivalence Check or LEC.
- Expert level understanding of Power, Performance, and Area (PPA) optimization techniques.
- Hands-on experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design.
- Ability to drive/manage projects from RTL to GDS, with experience managing 5-10+ tape-outs.
- Proficiency in physical design industry-standard EDA tools like Fusion compiler/ICC2/Primetime/Redhawk/PTPX, low power, and physical verification tools.
Nice to have
- Expert level understanding of EDA tools across Synopsys and Cadence.
- Latest use of AI technologies.
- Good understanding of foundry DRM and collaboration experience with DTCO and FTO.
- B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering.
Skills: RTL2GDSII, Physical Design, Timing closure, PnR, Physical Verification
More semiconductor jobs: AMD jobs · Physical design jobs · India jobs
This role has been open 43 days — well below the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
708
|
Median days open
63 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (708 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 60 | 708 |
| Open roles in the wider Physical Implementation family | 85 | 1591 · 117 employers |
| Median days open | 37 d | 63 d (−26 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL2GDSII, Physical Design, Timing closure, PnR, Physical Verification
Who's hiring in this category
- Qualcomm · 109 open roles · median 57 d
- AMD (this employer) · 61 open roles · median 37 d
- Broadcom · 49 open roles · median 37 d
- NVIDIA · 45 open roles · median 78 d
- Synopsys · 43 open roles · median 36 d
- Intel Corporation · 33 open roles · median 27 d
How we counted: 708 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.