PCIe ASIC Design Engineer

PCIe controllers

About the role

What you'll do

• Own end-to-end integration of PCIe IP into complex ASIC designs.
• Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
• Drive performance optimization efforts across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency.
• Lead silicon bring-up and validation of PCIe links in the lab.
• Debug functional and performance issues at RTL, gate-level, and silicon.
• Ensure compliance with PCIe specifications and participate in interoperability testing.

What you'll need

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of industry experience in ASIC/SoC design with a focus on PCIe controller integration.
• Proven experience in silicon bring-up and debug of high-speed interfaces.
• Solid understanding of PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space, and link training.
• Hands-on experience with PCIe verification environments, performance tuning, and power-aware design.
• Familiarity with PCIe compliance testing, simulation tools (e.g., VCS, Questa) and lab equipment (e.g., protocol analyzers, oscilloscopes), and scripting (Python, Perl, TCL).

Nice to have

• Experience with PCIe Gen5/Gen6 and advanced retimer or switch solutions.
• Exposure to CXL, CCIX, or other cache-coherent interconnects.
• Background in data center or AI/ML accelerator architectures.
• Experience with emulation and prototyping platforms (e.g., ZeBu, Palladium, HAPS) for PCIe subsystem validation.

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