PCB Layout Engineer - San Jose, United States
Originally posted 11 June 2025 by the employer — open 456 days.
About the role
This role involves designing and optimizing printed circuit boards (PCBs) for high-performance data center products, with a focus on high-speed signaling, power distribution, and complex HDI PCB stack-ups.
What you'll do
- Lead the design and optimization of high-speed PCB layouts using Cadence Allegro, tailored for 100G signaling.
- Implement strategies for impedance matching, trace routing, and crosstalk mitigation.
- Develop and implement power distribution networks, including power planes, decoupling strategies, and thermal management solutions.
- Manage the design of complex High-Density Interconnect (HDI) PCB stack-ups for multi-layer boards, integrating blind/buried vias and microvias.
- Collaborate with electrical and mechanical engineering teams to integrate PCB designs within the overall system architecture.
What you'll need
- Bachelor’s degree in Electrical Engineering, Electronics Engineering, or a related field.
- 10 years of experience in PCB layout design with a focus on high-speed signaling, power distribution, and HDI stack-ups.
- Proficiency in Cadence Allegro PCB design tools.
- In-depth knowledge of high-speed digital design principles, including signal integrity and impedance control.
- Experience with complex HDI PCB design and manufacturing processes.
- Understanding of power distribution network design and thermal management techniques.
Skills: PCB layout, 100G signaling, impedance matching, Cadence Allegro, HDI PCB, power distribution network
This role has been open 178 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 2 | 217 |
| Median days open | 155 d | 91 d (+64 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: PCB layout, 100G signaling, impedance matching, Cadence Allegro, HDI PCB, power distribution network
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.