Package & SI/PI - Signal and Power Integrity Engineer - Vancouver, BC OR Bay Area, CA, United States
Originally posted 5 May 2023 by the employer — open 1223 days.
About the role
This role involves providing packaging solutions for chiplet interconnects.
What you'll do
- Work closely with analog circuit designers to understand and define IO requirements co-designed with the channel.
- Perform pre-layout and post-layout channel simulation and optimization.
- Use driver/receiver models to run transient channel simulation, inspect eye diagrams, and improve performance.
- Apply best practices for the design of power delivery networks, extracting models, and performing DC/AC/transient simulations.
- Understand substrate and interposer manufacturing design rules, assembly requirements, and drive layout engineers.
- Perform measurements in the lab, correlate with simulation, identify issues, and provide solutions.
What you'll need
- Expertise in signal integrity and power integrity simulation methodologies.
- Experience with simulation tools such as HFSS, Q3D, Siwave, PowerDC, PowerSI, ADS, Spectre, HSPICE, Allegro.
- Knowledge of using lab equipment such as Vector Network Analyzer, Spectrum Analyzer, High-Frequency Oscilloscope.
- BS degree in EE or equivalent, with 5 years of experience.
Skills: signal integrity, power integrity, channel simulation, power delivery networks, SerDes design
This role has been open 77 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Eliyan | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 2 | 1317 · 100 employers |
| Median days open | 77 d | 91 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: signal integrity, power integrity, channel simulation, power delivery networks, SerDes design
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.