Package Layout Engineer - Mountain View, CA, United States

Originally posted 6 August 2026 by the employer.

This role focuses on multi-die 2.5D and 3D packages.

About the role

This role involves owning the physical layout of advanced packages for AI accelerator silicon, specifically multi-die 2.5D and 3D packages.

What you'll do

• Own package substrate and interposer layout end to end, including stackup definition, bump and ball map planning, RDL and escape routing, and design release to substrate suppliers and OSATs.
• Own die-to-package-to-board co-design, partnering with physical design on bump placement and floorplan and with PCB layout on the package-board interface.
• Close package DRC/LVS and netlist verification against OSAT and substrate vendor design rules, and drive rule negotiation where the design requires it.

What you'll need

• Experience in advanced package physical layout, including multi-die substrate and interposer routing, high-density escape, power and ground plane design for high-current accelerator rails, and stackup and via structure definition.
• 8+ years of package layout experience on high-performance designs, including 2.5D / 3D and multi-die packages (CoWoS, EMIB, InFO, fan-out, or equivalent interposer technologies).
• Hands-on with industry-standard package layout tools (Cadence Allegro Package Designer / SiP Layout, Siemens Xpedition Package Designer, or equivalent) and package DRC/LVS flows.
• Demonstrated ability to work closely with architecture, physical design, SI/PI, thermo-mechanical, and OSAT partners to converge and sign off complex package designs.

Skills: package substrate layout, interposer layout, multi-die 2.5D and 3D packages, RDL and escape routing, Cadence Allegro Package Designer