Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging - Haifa, ISR, Israel
Originally posted 24 September 2026 by the employer.
About the role
This role involves the physical design of advanced IC packages for machine learning and data center ASICs, focusing on advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB).
What you'll do
- Execute package layout tasks across the design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
- Implement physical designs for advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies.
- Support package floorplan development considering die placement, bump maps, power/ground distribution, signal escape routing, and decoupling capacitor placement.
- Perform RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates or silicon interposers.
- Support die-level RDL routing and bump planning in coordination with ASIC physical design teams.
- Run physical verification checks (DRC, connectivity, shorts/opens) and support design closure.
What you'll need
- Experience with package layout tasks from floor planning through tape out and manufacturing release.
- Knowledge of advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB).
- Ability to support package floorplan development, including die placement, bump maps, power/ground distribution, and signal escape routing.
- Experience performing RDL and substrate routing for high-density interconnects (microbumps, C4 bumps, TSVs, microvias, PTH vias).
- Capability to run physical verification checks (DRC, connectivity, shorts/opens).
- Experience working with OSAT partners and foundries to ensure DFM compliance.
This role has been open 2 days — well below the 39-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
69
|
Median days open
39 d
|
Median salary
$173k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (69 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 69 |
| Median days open | 18 d | 39 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $173k |
Who's hiring in this category
- Micron Technology · 12 open roles · median 149 d
- AMD · 6 open roles · median 33 d
- Marvell Technology · 6 open roles · median 19 d
- Broadcom · 5 open roles · median 169 d
- Amazon (this employer) · 4 open roles · median 18 d
- Intel Corporation · 4 open roles · median 9 d
How we counted: 69 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 25 employers tracked in the SemiconductorJobs index, counted 27 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.