Focus on parallel optical links built from arrays of microLED transmitters and photodetector receivers.
About the role
Avicena is seeking a Package Integration and SI/PI Engineer to own the boundary between the ASIC and its package. The role supports parallel optical links built from arrays of microLED transmitters and photodetector receivers.
What you'll do
- Own the die-package boundary for the ASIC, including bump and pad map inputs along with signal and power assignment with the package team.
- Perform signal integrity analysis of high-speed and clock paths across die, package, and board, including channel extraction, crosstalk, and return paths.
- Perform power integrity analysis from die through package to board, covering impedance targets, supply noise and ripple, and on-die and package decoupling.
- Build and exchange chip power and package models, and run die-package co-simulation with the chip team.
- Provide power maps for thermal analysis, and define ESD and supply strategy with core analog and layout teams.
- Run die/package feasibility reviews and correlate models with lab measurements.
What you'll need
- MS in Electrical Engineering (or BS with equivalent experience) and 5+ years of SI/PI work on high-speed ICs and packages.
- Experience with tools such as Ansys HFSS, SIwave and RedHawk, Cadence Sigrity and Clarity, or Keysight ADS.
- Strong grasp of S-parameters, TDR, transmission lines, and PDN design.
- Flip-chip package integration experience.
Nice to have
- 2.5D/3D or other advanced packaging experience.
- Optical or co-packaged optics modules experience.
- Lab measurement with VNA and oscilloscopes.
- Python or MATLAB automation.
Skills: SI/PI, HFSS, Sigrity, PDN design, die-package co-simulation
More semiconductor jobs: Advanced packaging jobs · Sunnyvale jobs
This role has been open 3 days — well below the 57-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
77
|
Median days open
57 d
|
Category median salary (all employers)
$176k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Avicena | All employers we track in this specialty (77 roles · 27 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 77 |
| Median days open | 3 d | 57 d (−54 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Skills observed across this category: SI/PI, HFSS, Sigrity, PDN design, die-package co-simulation
Who's hiring in this category
- AMD · 14 open roles · median 28 d
- Micron Technology · 9 open roles · median 191 d
- Marvell Technology · 6 open roles · median 36 d
- NVIDIA · 6 open roles · median 61 d
- Qualcomm · 5 open roles · median 81 d
- Broadcom · 3 open roles · median 99 d
How we counted: 77 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 27 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.