Package Design, Signal and Power Integrity Senior Staff Engineer
$141,150 - $211,400 USD yearly
Develop high-speed IC package SI/PI solutions for semiconductor packages supporting 448 Gb/s data rates and beyond.
Originally posted 5 October 2026 by the employer.
About the role
This role is responsible for high-speed IC package signal and power integrity design within Central Engineering, developing microelectronic packages for semiconductors supporting 448 Gb/s data rates and beyond.
What you'll do
- Execute package interconnect design, modeling, characterization, power delivery, and simulation methodology development.
- Drive SI/PI design from architecture through implementation, validation, and measurement correlation.
- Explore new interconnect architectures and develop design rules for custom high-speed interfaces lacking established methodologies.
- Investigate channel and PDN behavior systematically to identify and establish root cause.
- Collaborate with cross-functional teams to invent practical interconnect solutions and establish simulation workflows.
What you'll need
- MS or PhD in Electrical Engineering or Computer Engineering with relevant industry experience.
- Strong understanding of transmission line theory and EM fundamentals, along with frequency and time domain analysis in high-speed design.
- Hands-on experience using 2-D and 3-D EM simulation tools such as Ansys HFSS, SIwave, or Cadence Clarity.
- Experience with power plane design, modeling, and analysis using tools like PowerSI or SIwave.
- Working knowledge of channel and circuit simulators such as ADS and HSPICE.
- Experience with lab measurements and equipment including VNA and TDR.
- Familiarity with package layout tools such as Allegro, APD, or PADS.
Nice to have
- Experience with 2.5D/3D package development and high-speed electronic packaging for digital and analog ICs.
- Familiarity with packaging technologies, materials, package substrate design rules, and assembly rules.
- Knowledge of thermal and mechanical analysis in IC package development.
- Experience with CPC/CPO connectors.
- Ability to automate SI, PI, and packaging workflows using scripting tools such as Python.
Skills: IC package SI/PI, high-speed interfaces, 2.5D/3D package, EM simulation, transmission line theory
More semiconductor jobs: Marvell Technology jobs · Advanced packaging jobs · Santa Clara jobs
This role has been open 28 days — well below the 52-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
74
|
Median days open
52 d
|
Category median salary (all employers)
$176k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (74 roles · 26 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 74 |
| Median days open | 31 d | 52 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Skills observed across this category: IC package SI/PI, high-speed interfaces, 2.5D/3D package, EM simulation, transmission line theory
Who's hiring in this category
- AMD · 12 open roles · median 40 d
- Micron Technology · 10 open roles · median 184 d
- Marvell Technology (this employer) · 6 open roles · median 30 d
- NVIDIA · 6 open roles · median 55 d
- Qualcomm · 4 open roles · median 97 d
- Broadcom · 3 open roles · median 93 d
How we counted: 74 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 26 employers tracked in the SemiconductorJobs index, counted 2 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.