Package Design Principal Engineer - Bangalore, India
Originally posted 10 September 2026 by the employer — open 0 days.
About the role
This role involves driving microelectronic package development from concept through tapeout, ensuring manufacturability, performance, reliability, and cost compliance.
What you'll do
- Develop C4 and BGA ball maps optimized for SI/PI and layout efficiency.
- Plan and validate netlist mappings across dies, interposers, and substrates.
- Define die placement, padstacks, net assignments, and package-level connectivity.
- Create and maintain Package Requirement Documents (PRDs) detailing die arrangements, stackups, and design constraints.
- Contribute to tool, process, and flow development, including library maintenance and basic scripting for automation.
- Collaborate with chip and board design and electrical simulation teams for co-design and optimization.
What you'll need
- 13-16 years of related professional experience.
- Experience developing netlists and schematics for large, complex packages.
- Experience developing C4 and BGA ball maps for high-pin-count designs.
- Proficiency with design tools Cadence OrbitIO / Integrity System Planner (ISP) or equivalent.
- Strong foundational understanding of package design, including design rules, breakout, place and route, signal shielding, reference planes, power distribution, and pinout optimization.
- Solid grasp of SI/PI fundamentals at the substrate, board, and system levels.
- Knowledge of 2D, 2.5D, and emerging packaging architectures such as CoWoS-S/R/L, EMIB, CPO, and CPC.
- High-level understanding of thermal and mechanical package constraints (e.g., warpage, TIM).
- Familiarity with foundry design rules and substrate manufacturing constraints.
Nice to have
- Familiarity with running and interpreting signal and power simulations.
Skills: package design, C4, BGA, SI/PI, 2.5D, CoWoS
This role has been open 0 days — well below the 72-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
39
|
Median days open
72 d
|
Median salary
$222k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (39 roles · 18 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 39 |
| Median days open | 96 d | 72 d (+24 d vs this employer) |
| Median salary (USD postings) | — | $222k |
Skills observed across this category: package design, C4, BGA, SI/PI, 2.5D, CoWoS
Who's hiring in this category
- Qualcomm · 5 open roles · median 72 d
- AMD · 4 open roles · median 42 d
- Marvell Technology (this employer) · 4 open roles · median 107 d
- Micron Technology · 4 open roles · median 119 d
- NVIDIA · 4 open roles · median 31 d
- Amazon · 2 open roles · median 17 d
How we counted: 39 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 18 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.