Package Design Engineer - San Jose, CA, United States
About the role
This role involves the end-to-end design of IC packages for high-speed digital and data-center-class products, encompassing flip-chip, wirebond, and 2.5D/interposer platforms.
What you'll do
- Own end-to-end package design from feasibility studies through tapeout using Cadence Allegro Package Designer.
- Route and close high-speed signal nets such as UCIe, LPDDR/DDR, PCIe, Ethernet, and UFS, using controlled-impedance and length-matching techniques.
- Design and optimize power delivery networks (PDN) for IC packages, including plane splits, decoupling strategy, and via stitching.
- Partner with SI/PI engineering to iterate and harden package designs based on feedback.
- Drive DRC/DFM closure with substrate vendors and manage design review cycles through tapeout.
- Collaborate cross-functionally on warpage, CTE mismatch, and underfill selection for package robustness.
What you'll need
- Proficiency in Cadence Allegro Package Designer (APD) and associated package layout tools for flip-chip/wirebond packaging.
- Demonstrated ability to close package designs against SIPI (signal integrity / power integrity) feedback loops.
- Solid fundamentals in high-speed digital signal integrity (impedance control, length matching, via stub effects) and power delivery network design.
- 5+ years of relevant experience in IC package design.
- Bachelor's or Master's degree in Electrical/Mechanical/Electronics Engineering, or related field.
- Working knowledge of package-level SI/PI, thermal, and mechanical issues.
Nice to have
- Experience with Cadence SKILL or equivalent tool for design automation.
- Experience with 2.5D interposer design using Cadence Innovus/Integrity (or equivalent) for silicon interposer / RDL routing.
- Proficiency in Cadence Sigrity/Ansys HFSS/Keysight ADS for package level extraction/analysis of package/interconnect structures.
- Proficiency in Ansys IcePack/Cadence Celsius for package thermal simulation.
- Experience with advanced packaging, Cu Pillar bump technology, and fine-pitch UBM design.
- Working proficiency in Cadence PCB design tools (Allegro X/ PCB Editor / Design Entry HDL) for board-level layout and package-board co-design.
- Familiarity with JEDEC package reliability qualification standards and package-level thermal/mechanical simulation.
Skills: Cadence Allegro Package Designer, bump/ball map, substrate stack-up, high-speed signal nets, power delivery networks
This role has been open 10 days — well below the 37-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
67
|
Median days open
37 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | TYLsemi | All employers we track in this specialty (67 roles · 24 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 67 |
| Median days open | 10 d | 37 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Cadence Allegro Package Designer, bump/ball map, substrate stack-up, high-speed signal nets, power delivery networks
Who's hiring in this category
- Micron Technology · 13 open roles · median 142 d
- AMD · 6 open roles · median 26 d
- Marvell Technology · 6 open roles · median 12 d
- Broadcom · 5 open roles · median 162 d
- NVIDIA · 5 open roles · median 37 d
- Amazon · 4 open roles · median 25 d
How we counted: 67 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 24 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.