Package Design Engineer – Principal Engineer
$210,000 - $315,000 USD yearly
Originally posted 2 November 2026 by the employer.
About the role
Lead the package design team within CHS to establish package and system architecture for the Qualcomm Datacenter business unit. This role owns end-to-end package design strategy from concept through production, utilizing advanced 2.5D and 3D integration technologies.
What you'll do
- Own the end-to-end package architecture and design strategy for datacenter and high-performance compute (HPC) products through qualification, production ramp, and sustaining support.
- Drive architecture selection and configuration optimization for advanced multi-die packages, including 2.5D/3D integration, HBM, silicon interposers, silicon bridges, and high-density organic substrates.
- Lead chip-package-board co-design across silicon floorplans, die partitioning, bump maps, HBM and chiplet placement, package pinout, routing architecture, and power delivery.
- Guide Package/SiP physical design, layout optimization, design verification, tapeout, DRC/DFM/ERC signoff, and release readiness.
- Define package-level electrical requirements and ensure signal integrity and power integrity targets are met for interfaces such as HBM, UCIe, PCIe, DDR, and high-speed SerDes.
- Lead technical engagement with foundries, OSATs, substrate suppliers, and EDA vendors to define design rules, qualify technologies, and improve production yield.
What you'll need
- Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field with 8+ years of System/Package Design/Technology Engineering experience (or Master's with 7+ years, or PhD with 6+ years).
- Deep technical expertise in advanced semiconductor packaging, including multi-chiplet 2.5D/3D integration, HBM, silicon interposers, silicon bridges, Flip-Chip BGA, and high-density substrates.
- Experience with Cadence APD/SiP or Siemens Xpedition Package Designer, including Constraint Manager, design-rule definition, DRC, DFM, ERC, and package release flows.
- Competency in package SI/PI and electromagnetic design, including transmission-line behavior, crosstalk, return paths, S-parameters, RLGC models, PDN impedance, and decoupling strategies.
- Ability to guide analyses using package extraction and SI/PI tools such as XtractIM, PowerSI, HFSS, or Q3D.
- Working knowledge of package thermal-mechanical design, including warpage, stress, material interactions, thermal interfaces, and reliability failure mechanisms.
Nice to have
- Master's or Ph.D. with 15 years of relevant semiconductor and packaging experience.
- Experience owning 2.5D/3D multi-die package architecture from concept through production for high-power AI, HPC, server, accelerator, or networking products.
- Direct experience integrating compute SoCs or chiplets with HBM and delivering silicon interposer or silicon bridge solutions.
- Proven understanding of HBM, UCIe or other die-to-die interfaces, PCIe, DDR, and high-speed SerDes package-level SI/PI and layout implications.
- Experience with Calibre physical verification tools and establishing package signoff criteria.
Skills: 2.5D/3D, HBM, UCIe, Interposer, Multi-die package architecture
More semiconductor jobs: Qualcomm jobs · Advanced packaging jobs · San Diego jobs
This role has been open 0 days — well below the 96-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
42
|
Median days open
96 d
|
Category median salary (all employers)
$209k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (42 roles · 18 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 42 |
| Median days open | 118 d | 96 d (+22 d vs this employer) |
| Median salary (USD postings) | — | $209k |
Skills observed across this category: 2.5D/3D, HBM, UCIe, Interposer, Multi-die package architecture
Who's hiring in this category
- Marvell Technology · 6 open roles · median 52 d
- Intel Corporation · 5 open roles · median 40 d
- Micron Technology · 5 open roles · median 153 d
- AMD · 4 open roles · median 46 d
- NVIDIA · 4 open roles · median 82 d
- Qualcomm (this employer) · 3 open roles · median 126 d
How we counted: 42 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 18 employers tracked in the SemiconductorJobs index, counted 3 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.