Package Design Engineer - Bengaluru, India

About the role

This role involves the design of IC packages for high-speed digital and data-center-class products. You will drive package design from bump/ball map definition through substrate stack-up, routing, signal/power integrity closure, and tapeout.

What you'll do

• Own end-to-end package design in Cadence Allegro Package Designer (APD) for design feasibility studies through tapeout.
• Route and close high-speed signal nets (e.g. UCIe, LPDDR/DDR, PCIe, Ethernet, UFS) using controlled-impedance and length-matching techniques.
• Design and optimize power delivery networks (PDN) for IC package, including plane splits, decoupling strategy, and via stitching.
• Partner with SI/PI engineering to iterate and harden the package design based on feedback.
• Drive DRC/DFM closure with substrate vendors and manage design review cycles through tapeout.
• Collaborate cross-functionally with mechanical/thermal/reliability engineering on warpage, CTE mismatch, and underfill selection.

What you'll need

• Proficiency in Cadence Allegro Package Designer (APD) and associated package layout tools for flip-chip/wirebond packaging.
• Demonstrated ability to close package designs against SIPI (signal integrity / power integrity) feedback loops.
• Solid fundamentals in high-speed digital signal integrity (impedance control, length matching, via stub effects) and power delivery network design.
• 6+ years of relevant experience in IC package design.
• Bachelor's or Master's degree in Electrical/Mechanical/Electronics Engineering, or related field.

Nice to have

• Working knowledge of package-level SI/PI, thermal, and mechanical issues.
• Experience with Cadence SKILL or equivalent tool for design automation.
• Experience with 2.5D interposer design using Cadence Innovus/Integrity for silicon interposer / RDL routing.
• Proficiency in Cadence Sigrity/Ansys HFSS/Keysight ADS for package level extraction/analysis.
• Proficiency in Ansys IcePack/Cadence Celsius for package thermal simulation.
• Experience with advanced packaging, Cu Pillar bump technology, and fine-pitch UBM design.
• Working proficiency in Cadence PCB design tools (Allegro X/ PCB Editor / Design Entry HDL) for board-level layout and package-board co-design.
• Familiarity with JEDEC package reliability qualification standards and package-level thermal/mechanical simulation.
• Bonus tools: Cadence Allegro PCB, Cadence Sigrity (PowerDC, PowerSI), Ansys HFSS, Cadence Innovus (2.5D interposer), Keysight ADS.

Skills: Cadence Allegro Package Designer, flip-chip, wirebond, 2.5D/interposer, signal integrity, power integrity