NPU EMIR (PDN) Signoff Engineer, Senior - Bangalore, India
Physical Design & EDA
Originally posted 18 September 2026 by the employer — open 0 days.
About the role
This role involves planning, designing, optimizing, verifying, and testing electronic systems, circuits, and digital systems.
What you'll do
- Perform IR Signoff for High Performance DSP Cores.
- Conduct Signal EM & Power EM Signoff for High Performance DSP Cores.
- Develop PG Grid specifications for different DSP cores.
- Perform ESD Signoff for High Performance DSP Cores.
- Validate PG Grid using Grid Resistance & Secondary PG Resistance Checks.
- Validate IR Drops using Static IR, Dynamic IR Vless & VCD Checks for Die & Pkg Components.
- Collaborate with SOC and Packaging Teams on Bumps Assignments, RDL Enablement, and Pkg Routing Optimizations.
What you'll need
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field and 4+ years of Hardware Engineering experience; OR Master's degree in Computer Science, Electrical/Electronics Engineering, or related field and 3+ years of Hardware Engineering experience; OR PhD in Computer Science, Electrical/Electronics Engineering, or related field and 2+ years of Hardware Engineering experience.
- 2 to 5 years of experience.
- Hands-on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level.
- Good understanding of Power Integrity Signoff Checks.
- Proficient in scripting languages (Tcl and Perl).
- Familiarity with Innovus for RDL / Bump Planning.
Nice to have
- Good knowledge on PD.
Market context
This role has been open 0 days — well below the 86-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
680
|
Median days open
86 d
|
Median salary
$197k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (680 roles · 73 employers) |
|---|---|---|
| Open roles in this specialty | 37 | 680 |
| Open roles in the wider Physical Implementation family | 155 | 1388 · 105 employers |
| Median days open | 70 d | 86 d (−16 d vs this employer) |
| Median salary (USD postings) | — | $197k |
Who's hiring in this category
- Cadence Design Systems · 173 open roles · median 141 d
- Synopsys · 52 open roles · median 58 d
- NVIDIA · 50 open roles · median 90 d
- Micron Technology · 36 open roles · median 119 d
- Qualcomm (this employer) · 36 open roles · median 72 d
- Intel Corporation · 29 open roles · median 23 d
How we counted: 680 open EDA/CAD Engineering (EDA Tools) roles from 73 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.