Mixed-Signal Verification Engineer - Sunnyvale, United States
Originally posted 20 October 2026 by the employer.
About the role
Apple is seeking a Mixed-Signal Verification Engineer to join the wireless silicon development team. The role focuses on verifying RF and mixed-signal blocks and their interfaces within a wireless SoC.
What you'll do
- Verify RF and mixed-signal blocks and their interfaces within the wireless SoC. - Interact with analog/RF design, digital DV, digital design, and wireless system teams to develop verification methodologies. - Build mixed-signal testbenches, checkers, and tests using SystemVerilog. - Balance verification coverage and time-to-tapeout trade-offs to ensure silicon-correct functionality.
What you'll need
- Bachelor's degree in a technical discipline. - Industry verification experience with RF/Mixed-Signal blocks and SOCs. - Experience building Mixed-Signal testbenches, checkers, and tests using System Verilog. - Experience with UVM methodology and HDL (System Verilog, Verilog) for verification. - Understanding of common analog/RF blocks. - Experience with UPF, Python, or Matlab. - Experience with Virtuoso Composer, ADE, and HED.
Nice to have
- 2+ years of relevant industry experience. - Experience creating and using real-numbered analog behavioral models in System Verilog. - Wireless domain experience.
Skills: SystemVerilog, UVM, Mixed-Signal, RF, Virtuoso
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1214
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1214 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 34 | 1214 |
| Open roles in the wider Digital Design & Verification family | 96 | 3244 · 116 employers |
| Median days open | 5 d | 64 d (−59 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: SystemVerilog, UVM, Mixed-Signal, RF, Virtuoso
Who's hiring in this category
- Qualcomm · 113 open roles · median 40 d
- AMD · 96 open roles · median 53 d
- NVIDIA · 84 open roles · median 61 d
- Synopsys · 65 open roles · median 35 d
- SiFive · 55 open roles · median 77 d
- Cadence Design Systems · 50 open roles · median 119 d
How we counted: 1214 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.