Mixed-Signal Design Verification Engineer - Cork, Ireland.
Analog & Mixed-Signal Design
Originally posted 25 May 2026 by the employer — open 108 days.
About the role
This role involves mixed-signal design verification for Mixed-Signal PHY IP. The work focuses on the latest Snapdragon SoCs using 3nm and below technology nodes, specifically for DDR, USB, PCIe, eDP, DPRX, HDMI, SGMII, DSI, CSI, and PLL IP.
What you'll do
- Perform SV/UVM based Design Verification of SerDes, DDR & PLL Mixed-Signal PHY IP.
- Collaborate with analog and digital front-end design teams to verify RTL and Analog/Mixed-Signal Designs.
- Interact with architecture, design, physical design, software, test, and SoC teams to verify and integrate IP designs.
- Develop unit and SoC/IP level test benches using UVM.
- Develop and execute constrained random functional verification environments in System Verilog/UVM.
- Provide post silicon ATE/PTE vector bringup and bench characterization support.
What you'll need
- Bachelor's degree in Engineering, Computer Science or related field.
- 2 years design verification or related work experience.
- Experience in design and verification of hardware and software on SoCs.
- Experience with SoC/IP Methodologies for verifying complex units using industry standard tools and technologies.
- Knowledge in developing unit and SoC/IP level test benches using UVM.
- Experience with constrained random functional verification environment in System Verilog/UVM.
- Experience in Low power verification using UPF at RTL and GLS simulation level.
- Experience in Power Aware Gate Level Simulation (GLS) verification flow with zero delay and SDF annotated simulation.
- Experience of pre and post-silicon verification testflow and automated test benches.
- Knowledge of test-plan development, coverage (code/functional) analysis, transaction level modelling, constrained random verification, assertion based and formal verification techniques with System Verilog.
- Experience with Verilog, SystemVerilog, Assertions, Python/TCL/Perl/shell-scripting.
Nice to have
- Emulation experience along with SV/UVM based simulation.
- Experience in analog mixed signal verification techniques.
Skills: SV/UVM, Mixed-Signal PHY, SerDes, DDR, PLL
Market context
This role has been open 107 days — well above the 79-day median for Mixed-Signal Design roles.
Mixed-Signal Design · Mixed Signal
|
Open roles in category
173
|
Median days open
79 d
|
Median salary
$178k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (173 roles · 44 employers) |
|---|---|---|
| Open roles in category | 10 | 173 |
| Median days open | 55 d | 79 d (−24 d vs this employer) |
| Median salary (USD postings) | — | $178k |
Skills observed across this category: SV/UVM, Mixed-Signal PHY, SerDes, DDR, PLL
Who's hiring in this category
- Analog Devices · 25 open roles · median 117 d
- Infineon Technologies · 14 open roles · median 71 d
- NVIDIA · 12 open roles · median 51 d
- SiTime · 11 open roles · median 169 d
- Qualcomm (this employer) · 10 open roles · median 55 d
- Microchip Technology · 8 open roles · median 168 d
How we counted: 173 open Mixed-Signal Design (Mixed Signal) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.