Mid-End ASIC Engineer, Senior

Own synthesis methodology, SDC constraints, and timing closure for AI accelerators at 5nm and below.

About the role

Senior Mid-End ASIC Engineer responsible for owning synthesis, timing convergence, implementation readiness, and logical design quality across our AI accelerator roadmap. You will serve as the technical bridge between architecture, RTL, verification, and physical implementation.

What you'll do

• Define and own synthesis methodology across ASIC generations, including scalable flows for RTL synthesis, constraint development, timing budgeting, QoR optimization, incremental synthesis, and hierarchical implementation.
• Own hands-on synthesis and constraint development using EDA tools such as Cadence Genus and Synopsys Design Compiler, maintaining SDC constraints, clock definitions, false paths, multicycle paths, generated clocks, and MMMC environments.
• Lead logical timing closure across frequency, area, power, congestion, and wireability, performing root-cause analysis of timing bottlenecks and developing timing budgets across partitions.
• Partner with backend implementation engineers to drive physical-aware synthesis, retiming, register balancing, pipeline optimization, logic restructuring, and hierarchical timing budgeting.
• Serve as the synthesis technical lead with external implementation partners, reviewing QoR, timing, area reports, and constraint methodology, and defining acceptance criteria.
• Apply AI to improve timing analysis, QoR regression, constraint generation, timing debug, report analysis, documentation, and engineering automation.

What you'll need

• 12+ years of ASIC implementation experience, including multiple successful tapeouts.
• Expert-level proficiency in synthesis methodology, flow development, and timing closure across complex, multi-million-gate designs.
• Expert-level command of Cadence Genus and/or Synopsys Design Compiler.
• Strong SDC expertise, including constraint development and MMMC environments.
• Hands-on experience with advanced process nodes at 5nm and below.
• Strong Tcl and Python scripting ability for automation and flow development.
• A BS or MS in Computer Science, Electrical Engineering, Computer Engineering, or a related field, or equivalent professional experience.

Nice to have

• Experience with AI accelerators, CPUs, or GPUs.
• Familiarity with LPDDR, PCIe, or SerDes interfaces.
• Exposure to chiplet-based architectures and multi-clock SoC designs.

Skills: synthesis methodology, timing closure, SDC constraints, physical-aware optimization, EDA tools

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