Memory Layout Manager - Bangalore, India
$181,000 - $308,000 USD yearly
Originally posted 16 September 2026 by the employer — open 2 days.
About the role
This role involves leading a team of layout engineers in delivering SRAM, RF, ROM, and CAM memory compiler designs. The scope includes optimized floorplanning, high-density placement and routing, and rigorous physical sign-off processes for FinFETs and GAA technologies.
What you'll do
- Lead and mentor a team of layout design engineers for memory compiler designs on FinFETs/GAA technologies.
- Oversee the design, development, modification, analysis, and verification of memory compiler layout designs.
- Provide technical guidance for analog, digital, memory, and standard cell layout methodologies, compilers, tools, and flows.
- Enable teams to execute by setting clear objectives and facilitating productive workflows through AI-driven EDA tools and generative machine learning models.
- Drive team results by inspiring and developing team members and fostering a supportive and collaborative environment.
- Manage resources effectively to optimize project execution and meet performance targets.
What you'll need
- Bachelor's or Master's degree in Electronics, Electrical, or VLSI Engineering with 15+ years of experience in memory compiler layout design and management.
- Proven track record of successful tape-outs on foundry geometries (e.g., 3nm, 2nm) using Cadence Virtuoso, Siemens Calibre, and Synopsys IC Validator.
- Expert-level proficiency in driving layout methodologies and flows for analog, digital, memory, and standard cells.
- Demonstrated ability to lead teams and manage complex projects effectively.
Nice to have
- Experience in strategic decision-making and performance management for technical teams.
Skills: layout design engineering manager, memory compiler designs, FinFETs, GAA technologies, DRC, LVS, Yield, Cadence Virtuoso, AI and ML technologies
This role has been open 2 days — well below the 85-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
671
|
Median days open
85 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (671 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 29 | 671 |
| Open roles in the wider Physical Implementation family | 46 | 1371 · 106 employers |
| Median days open | 24 d | 85 d (−61 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: layout design engineering manager, memory compiler designs, FinFETs, GAA technologies, DRC, LVS, Yield, Cadence Virtuoso, AI and ML technologies
Who's hiring in this category
- Cadence Design Systems · 168 open roles · median 147 d
- Synopsys · 55 open roles · median 58 d
- NVIDIA · 47 open roles · median 71 d
- Micron Technology · 36 open roles · median 117 d
- Qualcomm · 34 open roles · median 71 d
- Intel Corporation (this employer) · 29 open roles · median 24 d
How we counted: 671 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.