MAC Design Verification Engineer - San Diego, United States
Originally posted 27 October 2026 by the employer.
About the role
As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC.
What you'll do
- Verify pre-silicon RTL for wireless MAC and its interfaces across the wireless SoC. - Interact with DV methodologists, designers, and communication systems engineers to develop reusable testbenches and verification environments. - Deploy metric-driven verification methodologies to achieve coverage and design quality goals.
What you'll need
- Minimum requirement of a bachelor's degree. - Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion. - Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage. - Verification experience with one or more of the following: MAC, PHY, DMA, timer, AMBA bus and fabric, or encryption/decryption engine.
Nice to have
- 3+ years of verification experience of wireless/wired communication block/subsystem. - Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee. - Proficiency in shell, Python, and Perl scripting. - Experience with AI technologies in data mining/analysis. - Experience with Palladium/FPGA validation.
Skills: UVM, SystemVerilog, ASIC verification, coverage, MAC
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1277
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1277 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 67 | 1277 |
| Open roles in the wider Digital Design & Verification family | 146 | 3375 · 116 employers |
| Median days open | 7 d | 64 d (−57 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, ASIC verification, coverage, MAC
Who's hiring in this category
- Qualcomm · 112 open roles · median 42 d
- AMD · 92 open roles · median 57 d
- NVIDIA · 91 open roles · median 67 d
- Synopsys · 73 open roles · median 42 d
- SiFive · 56 open roles · median 81 d
- Apple (this employer) · 55 open roles · median 8 d
How we counted: 1277 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.