Lead SoC Performance & Power Engineer
Lead the architectural configuration, system-level simulation, and PPA optimization for chiplets integrating PCIe, UCIe, and Ethernet with NoC fabric.
About the role
As our Lead Performance architect, you will drive the architectural configuration, system-level simulation, and PPA optimization of the chiplet by using industry-standard ESL tools or developing in-house tools to integrate and calibrate high-speed I/O IPs such as PCIe, UCIe and Ethernet as well as NoC fabric into a system.
What you'll do
- Own PPA exploration and trade-offs between peak performance, silicon area, and thermal/power budgets, turning them into tape-out recommendations.
- Build transaction-level models (TLM) using commercial ESL suites (e.g., Platform Architect) that integrate third-party IPs such such as PCIe, UCIe, and NoC into a full-chiplet model.
- Define, sweep, and validate hardware configuration parameters—buffer sizes, queue depths, clock-domain crossings, routing tables—to maximize throughput and minimize latency.
- Characterize traffic across the internal NoC and the UCIe die-to-die interface to find congestion points and rule out protocol deadlocks.
- Work directly with IP vendors to debug model/behavioral mismatches, report performance anomalies, and integrate new IP deliverables.
What you'll need
- BS/MS in Electrical Engineering or related field with 6+ years in computer architecture, performance modeling, or microarchitecture configuration.
- Direct, hands-on experience with commercial ESL tools such as Platform Architect, Virtualizer, or comparable frameworks.
- Solid working knowledge of at least one of: PCIe (Gen 5/6/7), UCIe, or AMBA NoC protocols (AXI/CHI).
- Strong Python for automating large-scale simulation sweeps, parsing performance reports, and analyzing results.
- Familiarity with SystemC and transaction-level modeling paradigms, including writing custom traffic generators.
Nice to have
- Fluency with power modeling or floor-planning trade-offs.
- Prior work on a multi-die / chiplet program, or hands-on UCIe die-to-die.
- Experience taking architectural models through to a real tape-out.
Skills: performance architect, PPA optimization, ESL tools, PCIe, UCIe, NoC
More semiconductor jobs: SoC design jobs · San Jose jobs
This role has been open 79 days — exactly the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
485
|
Median days open
79 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | TYLsemi | All employers we track in this specialty (485 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 485 |
| Open roles in the wider Digital Design & Verification family | 22 | 3525 · 120 employers |
| Median days open | 79 d | 79 d (same as this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: performance architect, PPA optimization, ESL tools, PCIe, UCIe, NoC
Who's hiring in this category
- Qualcomm · 78 open roles · median 88 d
- NVIDIA · 67 open roles · median 81 d
- AMD · 39 open roles · median 68 d
- Arm Holdings · 29 open roles · median 11 d
- Apple · 28 open roles · median 12 d
- Micron Technology · 20 open roles · median 111 d
How we counted: 485 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.