Lead PDN EMIR Engineer - Bangalore, India
Originally posted 24 September 2026 by the employer.
About the role
This role involves owning full-chip and subsystem-level PDN signoff for complex SoCs.
What you'll do
- Own full-chip and subsystem-level PDN signoff for complex SoCs.
- Drive power integrity closure for functional, DFT, LBIST, capture, and stress modes.
- Lead package-aware IR/EM analysis and chip-package co-optimization.
- Define and review power grid architecture, bump planning, power switch strategy, and decap methodology.
- Develop PDN signoff methodologies and automate PDN flows using TCL/Python/Shell.
- Collaborate with Physical Design, DFT, Package, and Thermal teams on PDN-aware solutions, pattern power optimization, and RLC optimization.
What you'll need
- B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, or related field.
- 8+ years of experience in Physical Design, Power Integrity, or Signoff.
- Experience in full-chip and subsystem-level PDN signoff.
- Experience with IR/EM analysis.
- Knowledge of power grid architecture, bump planning, power switch strategy, and decap methodology.
- Experience with Vmin, peak EM, dynamic IR, and thermal-aware analysis.
- Proficiency in TCL/Python/Shell for automation.
- Experience collaborating with EDA vendors (Ansys/Cadence/Synopsys).
Skills: PDN signoff, IR/EM analysis, power integrity, floorplanning, DFT
This role has been open 0 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
630
|
Median days open
61 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (630 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 630 |
| Open roles in the wider Physical Implementation family | 45 | 1417 · 108 employers |
| Median days open | 78 d | 61 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: PDN signoff, IR/EM analysis, power integrity, floorplanning, DFT
Who's hiring in this category
- Qualcomm · 123 open roles · median 37 d
- NVIDIA · 39 open roles · median 48 d
- Broadcom · 38 open roles · median 73 d
- AMD · 35 open roles · median 43 d
- Synopsys · 27 open roles · median 62 d
- Cadence Design Systems · 23 open roles · median 87 d
How we counted: 630 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 24 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.