Lead Analog SerDes Architect/Design Engineer - California, Santa Clara, United States
$220,920 - $311,890 USD yearly
Originally posted 7 January 2026 by the employer — open 246 days.
This role focuses on integrated silicon photonics for high-speed connectivity.
About the role
This role involves defining circuit architecture and enabling designs for optical interconnects based on system specifications. You will contribute to the development of integrated circuit components for silicon photonics integration.
What you'll do
- Define circuit architecture and enable designs for optical interconnects.
- Work collaboratively leading block level development of integrated circuit components.
- Specify, architect, and design low voltage and low power Mixed-Signal integrated circuits.
- Plan design work considering performance, schedule, and quality.
- Provide guidance to junior designers and layout engineers.
- Guide the development of test plans for post-silicon characterization.
- Document all design work with review materials and detailed design descriptions.
What you'll need
- MS in Electrical Engineering with 8+ years of experience in high-speed serial links.
- Deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies.
- Hands-on circuit design experience of SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR for 28Gbps+ data rates.
- Experience with design of inductors, transmission line, Trans-Impedance Amplifiers (TIA), and modulator drivers.
- Experience with design of precision analog circuits like ADC/DACs.
- Experience with designing PAM4/NRZ links.
- Experience with Mixed signal design flow.
- Experience with full-chip designs, ESDs, and verification flows.
Nice to have
- Familiarity with Optical communications.
- Experience with 400G/800G/1.6T optical links.
- Experience with package/test setup design.
Skills: SerDes, analog CMOS, mixed-signal, optical interconnect, photonics integration
This role has been open 176 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 7 | 217 |
| Median days open | 132 d | 91 d (+41 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SerDes, analog CMOS, mixed-signal, optical interconnect, photonics integration
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.