Lead Analog Layout Design Engineer - CORK 01, Ireland
Originally posted 20 August 2026 by the employer.
About the role
This role is for a Lead Analog Layout Design Engineer who will take on a technical leadership position within the custom layout design team, focusing on SERDES products.
What you'll do
- Design high-speed SERDES for UCIe products at data rates up to 64 Gbps on 2nm FinFET CMOS technology nodes.
- Produce quality layouts of analog/mixed-signal circuit blocks in collaboration with circuit designers.
- Manage the back-end flow, from initial floor planning through detailed layout and final verification against foundry design rules.
- Provide technical leadership in layout design, from block level to PHY top-level integration and sign-off.
- Collaborate with global teams across different time zones.
What you'll need
- Minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC layout design and development.
- Proficient layout design experience with SERDES circuit blocks including Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, and Voltage Regulators.
- Ability to implement high speed and high accuracy cells, blocks, and IP blocks efficiently.
- Experience working with custom layout designers globally to build high-quality IP and test chips.
- Experience working with circuit designers and project managers globally to understand technical and schedule needs.
- BEng, MEng or PhD degree.
Skills: SERDES, high-speed I/O, layout design, FinFET CMOS, Cadence, 64 Gbps
This role has been open 40 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 29 | 1385 · 107 employers |
| Median days open | 181 d | 76 d (+105 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: SERDES, high-speed I/O, layout design, FinFET CMOS, Cadence, 64 Gbps
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems (this employer) · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.