Lead Analog IC Designer - San Jose, United States
$114,800 - $213,200 USD yearly
Originally posted 14 May 2026 by the employer — open 119 days.
About the role
This role involves the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.
What you'll do
- Design and develop analog/mixed signal IC circuit blocks.
- Perform final verification of conformance to customer specifications.
What you'll need
- Minimum of 3 years of experience in CMOS SerDes or high-speed I/O IC design and development.
- Proficient design experience in Driver, Receiver, Serializer, Deserializer, Phase Interpolator, PLL, High Speed Clock Distribution, ADC and DAC, Bias and Bandgap, and Voltage Regulators.
- Excellent problem solving skills.
- Analog aptitude.
- Proficiency in using CAD tools for circuit simulation, layout, and physical verification.
- MS or PhD in EE.
Nice to have
- Working knowledge of common SerDes standards and their electrical requirements.
- Cadence tool experience.
- Lab test experience.
- Design experience at >112Gbps.
- Design experience in <7nm technologies.
Skills: SerDes, high-speed I/O, Driver, Receiver, Serializer, Deserializer
This role has been open 169 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 19 | 217 |
| Median days open | 153 d | 91 d (+62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SerDes, high-speed I/O, Driver, Receiver, Serializer, Deserializer
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems (this employer) · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.