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Synopsys

Layout Design Engineer

Synopsys img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Da Nang, Vietnam 23 days ago
Physical Design & EDA

Originally posted 12 September 2026 by the employer — open 8 days.

About the role

This Layout Design Engineer position focuses on custom layout of Analog IPs, including High Speed IOs, PLL, DLL, Bandgap, and High Speed macros for PHY.

What you'll do

  • Work on custom layout of Analog IPs like High Speed IOs, PLL, DLL, Bandgap, and High Speed macros for PHY, and Clock trees.
  • Perform floor planning, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics.
  • Conduct layout verification for DRC, LVS, ERC, ANT, ESD, and DFM.
  • Complete all design quality checks and data quality checks.
  • Report design status to mentors and design leads.
  • Create required documents for given tasks.

What you'll need

  • BS in Electronics Engineering, Electromechanics, or Telecommunications.
  • Interested in IC design and desire to pursue a long-term career path in IC design.
  • Good English communication verbally and in writing.
  • Good team player.
  • Highly responsible.
  • Self-motivated.

Nice to have

  • 1-2 years of experience in related fields of IC designs.

Skills: custom layout, High Speed IOs, PLL, DRC/LVS, Floor planning

Market context

This role has been open 4 days — well below the 59-day median for Physical Design roles.

Physical Design · Physical Design

Open roles in category
604
Median days open
59 d
Median salary
$185k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Synopsys compares in Physical Design hiring
Metric Synopsys All employers we track in this specialty (604 roles · 79 employers)
Open roles in this specialty 27 604
Open roles in the wider Physical Implementation family 87 1373 · 107 employers
Median days open 58 d 59 d (−1 d vs this employer)
Median salary (USD postings) — $185k

Skills observed across this category: custom layout, High Speed IOs, PLL, DRC/LVS, Floor planning

Who's hiring in this category

  • Qualcomm · 108 open roles · median 42 d
  • NVIDIA · 39 open roles · median 44 d
  • Broadcom · 38 open roles · median 69 d
  • AMD · 35 open roles · median 39 d
  • Synopsys (this employer) · 27 open roles · median 58 d
  • Renesas Electronics · 25 open roles · median 46 d

How we counted: 604 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.

Synopsys

Synopsys

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img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Da Nang, Vietnam
On-site
23 days ago

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