IO / Analog Design Engineer – High Speed Memory Interfaces (m/f/d) - Munich (MDC), Germany
€89,000 - €150,000 EUR yearly
Originally posted 8 June 2026 by the employer — open 93 days. Relisted by the employer on 7 September 2026.
About the role
What you'll do
- Define and own IO and PHY concepts for high-speed memory interfaces.
- Perform block-level simulation, analysis, and feasibility checks.
- Review and guide schematic-level implementation to align with architectural intent.
- Support verification, silicon bring-up, and debug activities.
- Collaborate with global cross-functional teams to ensure accurate system integration.
- Use AI automation and AI-based tools to improve modeling and analysis workflows.
What you'll need
- Demonstrated ability designing mixed-signal IO blocks, including schematic design and simulation.
- Proficiency with SPICE or similar circuit simulation tools.
- Hands-on experience with Cadence or Synopsys schematic entry environments.
- Ability to understand, model, and evaluate block-level behavior.
- Experience working in Unix/Linux environments.
Nice to have
- Scripting skills (Python, TCL, SKILL, Perl or similar) for analysis or automation.
- Familiarity with extraction and modeling tools.
- Experience collaborating with cross-functional design teams in a semiconductor environment.
Skills: IO and PHY concepts, high-speed memory interfaces, block-level simulation, schematic-level implementation, SPICE, Cadence, Synopsys
This role has been open 127 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 8 | 217 |
| Median days open | 115 d | 91 d (+24 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: IO and PHY concepts, high-speed memory interfaces, block-level simulation, schematic-level implementation, SPICE, Cadence
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.