Internship - Communication System Modelling - Saint-Sulpice
About the role
This internship focuses on investigating circuit and signal-processing techniques to enable simultaneous bidirectional communication over wideband copper serial links.
What you'll do
- Develop behavioural models of wideband copper channels and transceiver architectures.
- Study self-interference cancellation techniques in the analog and/or digital domains.
- Evaluate the impact of channel impairments, mismatch, and non-idealities on link performance.
- Design and simulate key building blocks using Python or circuit-level CAD tools.
- Assess achievable data rates, energy efficiency, and implementation complexity.
What you'll need
- Master's student in Electrical Engineering, Communications Engineering, or Computer Engineering.
- Understanding of the building blocks of a digital communication link and factors impacting the link performance.
- Strong background in signal processing.
- Strong background in communications.
- Proficient in at least one of the following programming languages: C++, MATLAB, or Python/NumPy.
Nice to have
- Familiarity with SerDes link components.
- Familiarity with clock recovery circuits.
Skills: high-speed serial interfaces, simultaneous bidirectional signalling, self-interference cancellation, wireline communication systems, transceiver architectures
This role has been open 86 days — below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Kandou | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 6 | 217 |
| Median days open | 98 d | 91 d (+7 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: high-speed serial interfaces, simultaneous bidirectional signalling, self-interference cancellation, wireline communication systems, transceiver architectures
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.