Intern - HBM SoC Physical Design Engineer - Folsom, CA, United States
$38 - $50 USD yearly
Originally posted 15 September 2026 by the employer — open 4 days.
This role focuses on implementing HBM SoC and base die designs.
About the role
This internship involves supporting the physical implementation of advanced HBM SoC designs. You will contribute to the development of memory products that power AI and high-performance computing applications.
What you'll do
- Support physical implementation of SoC design blocks, including floorplanning, placement, clock tree synthesis, routing, and physical optimization.
- Analyze timing, power, area, congestion, and physical verification results for design improvement.
- Assist with static timing analysis, timing closure, and debugging across operating modes and process corners.
- Develop and enhance automation tools, scripts, reports, and workflows using Python, Tcl, shell scripting, and AI-assisted solutions.
- Collaborate with engineering teams to document results, participate in design reviews, and present technical findings.
What you'll need
- 0-2 years of relevant experience through internships, research, coursework, or academic projects in ASIC design, VLSI, digital IC design, computer architecture, or physical design.
- Currently pursuing a Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- Knowledge of ASIC design flow concepts, including synthesis, place-and-route, static timing analysis, and physical verification.
- Understanding of timing fundamentals such as setup/hold analysis, clock skew, timing constraints, and critical path analysis.
- Experience with programming or scripting languages such as Python, Tcl, Perl, and/or Shell.
- Familiarity with AI-enabled tools and large language models (LLMs) such as Copilot, Claude, or similar technologies.
Nice to have
- Experience through coursework, research, or internships with RTL-to-GDSII implementation flows.
- Familiarity with industry-standard EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, or equivalent platforms.
- Knowledge of multi-mode, multi-corner timing analysis, power intent methodologies, power delivery networks, or IR/EM analysis.
- Understanding of DRC, LVS, parasitic extraction, signal integrity, clock tree synthesis, or congestion analysis concepts.
- Experience developing automation solutions, dashboards, or engineering workflows using Python, Tcl, or related scripting languages.
- Interest in HBM, DRAM, advanced packaging, memory-centric SoCs, or high-performance digital design.
Skills: physical implementation, floorplanning, placement, clock tree synthesis, routing, physical optimization
This role has been open 4 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
604
|
Median days open
59 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (604 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 20 | 604 |
| Open roles in the wider Physical Implementation family | 67 | 1373 · 107 employers |
| Median days open | 98 d | 59 d (+39 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: physical implementation, floorplanning, placement, clock tree synthesis, routing, physical optimization
Who's hiring in this category
- Qualcomm · 108 open roles · median 42 d
- NVIDIA · 39 open roles · median 44 d
- Broadcom · 38 open roles · median 69 d
- AMD · 35 open roles · median 39 d
- Synopsys · 27 open roles · median 58 d
- Renesas Electronics · 25 open roles · median 46 d
How we counted: 604 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.