Intern, Architect - Analysis of AI Workloads & Network Communication Protocols
$50 - $60 USD hourly
About the role
This graduate internship joins the architecture team within the Office of the CTO to deploy inference and agentic workloads on data center clusters and benchmark their performance. You will architect and develop specifications for network communication protocol stack layers in optical engines.
What you'll do
- Deploy inference and agentic workloads on data center clusters and benchmark their performance.
- Analyze AI models and resource requirements for training and inference operations.
- Architect and develop the specifications of network communication protocol stack layers in optical engines.
- Collaborate with senior engineers on projects tailored to optical I/O technology evaluation.
What you'll need
- Currently pursuing an M.S. or Ph.D. degree in Computer Engineering, Computer Science, Electrical Engineering, Mathematics, or equivalent.
- Experience deploying AI workloads on data center platforms and benchmarking performance.
- Familiarity with profiling and instrumentation tools such as Nvidia Nsight, Nsys, GPGPU-Sim, or LLVM-based tooling.
- Experience with memory semantic fabrics and network communication protocols such as AXI, CHI, UALink, ESUN, 802.3 Ethernet, UCIe, or PCIe.
Skills: AI workloads, optical I/O, network protocols, PCIe, UCIe, benchmarking
More semiconductor jobs: SoC design jobs · San Jose jobs
This role has been open 4 days — well below the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
485
|
Median days open
79 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ayar Labs | All employers we track in this specialty (485 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 485 |
| Open roles in the wider Digital Design & Verification family | 10 | 3525 · 120 employers |
| Median days open | 137 d | 79 d (+58 d vs this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: AI workloads, optical I/O, network protocols, PCIe, UCIe, benchmarking
Who's hiring in this category
- Qualcomm · 78 open roles · median 88 d
- NVIDIA · 67 open roles · median 81 d
- AMD · 39 open roles · median 68 d
- Arm Holdings · 29 open roles · median 11 d
- Apple · 28 open roles · median 12 d
- Micron Technology · 20 open roles · median 111 d
How we counted: 485 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.