Infra Systems Physical Architect
$140,000 - $210,000 USD yearly
Originally posted 5 January 2026 by the employer.
About the role
As a Physical Architect in the Infra Systems Architecture team, you will design floorplan-driven Network on Chip (NoC) architectures implemented for optimal PPA. The role focuses on connecting IPs such as CPU, GPUs, NSPs, and modems to DDR subsystems across complex SoCs.
What you'll do
- Architect, plan, and enable floorplan-driven NoCs to meet latency, area, performance, and power targets. - Analyze, review, and refine functional and test (DFT) mode constraints for synthesis and place-and-route processes. - Develop recipes for physical aware synthesis, custom placement strategies, optimal floorplanning, and special clocking solutions such as mesh clock trees. - Implement power planning, low-power analysis, and specialized routing techniques to reduce wire delays. - Execute timing optimization and timing closure with signal integrity for MMMC designs. - Automate flows and analyze architectural trade-offs using Python, PERL, TCL, Linux/Unix shell, and C.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 6+ years of ASIC design, verification, validation, integration, or related experience (or Master's with 5+ years, or PhD with 4+ years). - Experience with physical aware synthesis, floorplanning, and place-and-route workflows. - Hands-on experience developing timing constraints and achieving timing closure for MMMC designs. - Scripting and programming proficiency in Python, PERL, TCL, Linux/Unix shell, or C.
Nice to have
- 5 years of industry experience or coursework in NoC implementation, AMBA protocol, and cache coherency mechanisms. - Experience with physical aware DFT, clock tree planning spine, and mesh CTS. - Custom placement and routing and source sync clock routing experience. - Formal verification and power domain analysis experience. - Tool expertise in Design Compiler, Fusion Compiler, Genus, PrimeTime, PrimePower, or Innovus, alongside TCL programming in these environments.
Skills: NoC (Network on Chip), floorplan driven, PPA, physical aware synthesis, special placement strategies, floorplanning
This role has been open 200 days — well above the 65-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 123 | 673 |
| Open roles in the wider Physical Implementation family | 170 | 1491 · 109 employers |
| Median days open | 48 d | 65 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: NoC (Network on Chip), floorplan driven, PPA, physical aware synthesis, special placement strategies, floorplanning
Who's hiring in this category
- Qualcomm (this employer) · 124 open roles · median 48 d
- AMD · 63 open roles · median 27 d
- Intel Corporation · 40 open roles · median 17 d
- Synopsys · 37 open roles · median 39 d
- NVIDIA · 36 open roles · median 67 d
- Broadcom · 35 open roles · median 104 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.